Slide 1

Report
NSNI – 2010, Mumbai, India
Development of high speed
waveform sampling ASICs
Stefan Ritt - Paul Scherrer Institute, Switzerland
Question …
4 channels
5 GSPS
1 GHz BW
8 bit (6-7)
15k$ (700kRs)
Feb. 25th, 2010
4 channels
5 GSPS
1 GHz BW
11.5 bits
1k$ (50kRs)
USB Power
NSNI-2010 Mumbai
2
Switched Capacitor Array
0.2-2 ns
Inverter “Domino” ring chain
IN
Waveform
stored
Clock
Shift Register
Out
FADC
33 MHz
“Time stretcher” GHz  MHz
Feb. 25th, 2010
NSNI-2010 Mumbai
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Switched Capacitor Array
• Cons
Dt
Dt
Dt
Dt
Dt
• No continuous acquisition
• Limited sampling depth
• Nonlinear timing
• Pros
• High speed (up to 5 GSPS) high resolution (13 bit SNR)
• High channel density (16 channels on 5x5 mm2)
• Low power (10-40 mW / channel)
• Low cost (~ 10$ / channel)
Feb. 25th, 2010
NSNI-2010 Mumbai
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Design Options
• CMOS process (typically 0.35 … 0.13 mm)  sampling speed
• Number of channels, sampling depth, differential input
• PLL for frequency stabilization
• Input buffer or passive input
• Analog output or (Wilkinson) ADC
• Internal trigger
PLL
Trigger
ADC
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NSNI-2010 Mumbai
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Write Circuitry
How to sample the input signal
Simple inverter chain
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
0
0
1
1
1
1
1
0
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
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Design of Inverter Chain
PMOS > NMOS
PMOS < NMOS
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“Tail Biting”
speed
enable
1
2
3
4
1
2
3
4
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Phase Locked Loop
On-chip PLL can lock sampling frequency to external reference clock
Inverter Chain
sampling speed control
T Q
F1
PLL
up
Phase
Comparator down
External
Reference
Clock
Feb. 25th, 2010
loop
filter
F2
NSNI-2010 Mumbai
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Timing jitter
• Inverter chain has transistor
variations
 Dti between samples differ
 “Fixed pattern aperture jitter”
• “Differential temporal nonlinearity”
TDi= Dti – Dtnominal
• “Integral temporal nonlinearity”
TIi = SDti – iDtnominal
• “Random aperture jitter” = variation
of Dti between measurements
Dt1 Dt2 Dt3 Dt4 Dt5
TD1
Feb. 25th, 2010
TI5
NSNI-2010 Mumbai
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Fixed jitter calibration
• Fixed jitter is constant over time,
can be measured and corrected
for
• Several methods are commonly
used
• Most use sine wave with random
phase and correct for TDi on a
statistical basis
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Fixed Pattern Jitter Results
• TDi typically ~50 ps RMS @ 5 GHz
• TIi goes up to ~600 ps
• Jitter is mostly constant over time,
 measured and corrected
• Residual random jitter 3-4 ps RMS
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Achievable Timing Resolution
After proper timing calibration, a
“split pulse timing accuracy” of typically
~10 ps can be chieved
D. Breton
Picosecond Workshop
Clermont-Ferrand, Jan 2010
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What determines the BW?
• The analog bandwidth is given by the parasitic capacitance of the
input bus and the input impedance
• Typically 20fF/cell+20pF (bus), 2-3 W for bond wire  1 GHz BW
• An active input buffer does not really help
f 3dB 
1
 1.8 GHz
2RC
“The best buffer is no buffer”
– G. Varner
Feb. 25th, 2010
Bond wire
2-3 W
20 pF
20 fF
NSNI-2010 Mumbai
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Cascaded Switched Capacitor Array
• Combines the advantage of a short input stage (32 cells) with a
deep secondary sampling stage (32x32 cells)
• Estimated input BW:
5 GHz
input
shift register
• Sampling speed:
10 GSPS (130 nm)
• 100 ps sample time –
3.1 ns hold time
• Matches BW of fastest
detectors
(G-APD, MCP-PMT)
.................................
•  next generation of SCAs
fast sampling stage
Feb. 25th, 2010
NSNI-2010 Mumbai
secondary sampling stage
16
Readout Circuitry
How to read out sampled waveforms
Analog Readout Methods
Uin
“Differential
Pair”
write
read
Uin
Vout
C
read
write
(200fF)
R
I ~ kT
Uin
I
C
(700 W)
Ib/2
Ib/2
Ib
read
write
...
C
Feb. 25th, 2010
NSNI-2010 Mumbai
+
-
18
Digital Readout
Wilkinson-type ADC requires only one comparator per sampling cell
ramp voltage
+
comparator
+
-
comparator
-
latch
DAC
latch
12-bit counter
ASIC
FPGA
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How to minimize dead time ?
• Fast analog readout: 30 ns / sample
• Parallel readout
• Region-of-interest
readout
FUNCTIONAL BLOCK DIAGRAM
AGND AVDD DSPEED PLLOUT PLLLCK
PLL
WSRIN
DENABLE
DWRITE
REFCLK
LVDS
DOMINO WAVE CIRCUIT
IN0
DTAP A0 A1 A2 A3
MUX
ENABLE
• Simultaneous
write / read
DRS4
CHANNEL 1
OUT1
CHANNEL 2
OUT2
CHANNEL 3
OUT3
CHANNEL 4
OUT4
CHANNEL 5
OUT5
CHANNEL 6
OUT6
IN7
CHANNEL 7
OUT7
IN8
CHANNEL 8
IN1
IN2
IN3
IN4
IN5
IN6
WRITE SHIFT REGISTER
OUT0
WRITE CONFIG REGISTER
CHANNEL 0
WSROUT
STOP SHIFT REGISTER
RSRLOAD
SRIN
SRCLK
READ SHIFT REGISTER
MUX
AD9222
12 bit
8 channels
OUT8/
MUXOUT
O-OFS
BIAS
ROFS
SROUT
RESET
CONFIG REGISTER
DVDD DGND
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DRS4 ROI readout mode
delayed trigger
normal
stop
trigger stop after latency
Trigger
Delay
stop
33 MHz
e.g. 100 samples @ 33 MHz
 3 us dead time
 300,000 events / sec.
Feb. 25th, 2010
readout shift register
Patent pending!
NSNI-2010 Mumbai
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Simultaneous Write/Read
FPGA
0
1
Channel 0
0
1
Channel 1
1
0
Channel 2
0
Channel 3
0
Channel 4
0
Channel 5
0
Channel 6
0
Channel 7
readout
8-fold
analog multi-event
buffer
Expected crosstalk ~few mV
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Current SCA ASICs
Chip family
SAM [1]
LAB [2]
DRS [3]
Anusmriti [4]
Max. sampling speed
2.5 GSPS
3.7 GSPS
6 GSPS
0.5 GSPS
Analog Bandwidth
300 MHz
900 MHz
950 MHz
?
Number of channels
2
1-16
9
1
SNR
13.4 bits
10 bits
11.4 bits
?
Sampling depth
144-2520
256-64k
1025-8192
128
Readout time
650 ms
150 ms – 10ms
30 ns * nsamples
128 ms
Input Buffers
YES
YES
NO
YES
Internal PLL
YES
NO
YES
YES
ADC
External
Internal
External
External
Power/channel
150-500 mW
15-50 mW
14-45 mW
400 mW
[1]
[2]
[3]
[4]
E. Delagnes, D. Breton et al., NIM A567 (2006) 21
G. Varner et al., NIM A583 (2007) 447
S. Ritt, NIM A518 (2004) and http://drs.web.psi.ch
M. Sukhwani et al., NSNI 2010
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Advanced Topics
Triggering, Channel Cascading, Waveform Analysis
How to measure best timing?
Simulation of MCP with realistic noise and different discriminators
J.-F. Genat et al., arXiv:0810.5590 (2008)
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Flash ADC Technique
PMT/APD
Wire
Q-sensitive
Preamplifier
Baseline
Shaper Restoration
PMT/APD Transimpedance
Preamplifier
Wire
FADC
60 MHz
12 bit
Amplitude
TDC
Time
FADC
“Fast”
12 bit
•
•
•
•
Digital
Processing
Shaper is used to optimize signals for “slow” 60 MHz FADC
Shaping stage can only remove information from the signal
Shaping is unnecessary if FADC is “fast” enough
All operations (CFD, optimal filtering, integration) can be done digitally
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How fast is “fast”
• Nyquist-Shannon: Sampling rate must be 2x the highest
frequency coming from detector
• Analog Bandwidth must match signal from detector
• Fastest pulses coming from Micro-Channel-Plate PMTs
3mm
pores
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Fastest pulses
• MCP-PMTs: 70 ps rise time
 4-5 GHz BW  10 GSPS
input
shift register
• Cable should not limit bandwidth
 Put digitizer onto detector
Aimed parameters:
5 GHz Bandwidth
10 GSPS Sampling Rate
• Higher sampling speed only
improves statistics
.................................
fast sampling stage
secondary sampling stage
10 GSPS
30 GSPS
J. Milnes, J. Howoth, Photek
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NSNI-2010 Mumbai
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Trigger and DAQ on same board
• All SCA applications need some kind of trigger  split signals
DRS4
trigger
DRS
MUX
• DRS readout (5 GSPS)
though same 8-channel
FADCs
analog front end
• FPGA can make local trigger
(or global one) and stop DRS
upon a trigger
FADC
12 bit
65 MHz
FPGA
global trigger bus
• Using a multiplexer in DRS4, input signals can simultaneously digitized
at 65 MHz and sampled in the DRS
LVDS
SRAM
“Free” local trigger capability without additional hardware
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Daisy-chaining of channels
Domino Wave
clock
Domino Wave
clock
1
enable
input
Channel 0
0
enable
input
Channel 0
0
enable
input
Channel 1
1
enable
input
Channel 1
1
Channel 2
0
Channel 2
0
Channel 3
1
Channel 3
1
Channel 4
0
Channel 4
0
Channel 5
1
Channel 5
1
Channel 6
0
Channel 6
0
Channel 7
1
Channel 7
DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cells
Chip daisy-chaining possible to reach virtually unlimited sampling depth
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Interleaved sampling
delays (167ps/8 = 21ps)
6 GSPS * 8 = 48 GSPS
G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007)
Possible if delay is implemented on PCB
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On-line waveform display
S848
PMTs
“virtual oscilloscope”
template
fit
click
pedestal
histo
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Pulse shape discrimination
Example: a/g source in liquid xenon detector (or: g/p in air shower)
a
g
(t  t 0 ) /τ s
(t  t 0 )/τ d 
 (t  t 0 ) /τi
V(t)  A e
 Be
 Ce
θ(t  t 0 )  [...]θ..  t 0  t r )


Leading edge
Feb. 25th, 2010
Decay time
AC-coupling
NSNI-2010 Mumbai
Reflections
33
t-distribution
ta = 21 ns
tg = 34 ns
a
Waveforms can
be clearly
distinguished
g
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Template Fit
• Determine “standard” PMT pulse by
averaging over many events  “Template”
b Experiment
500 MHz sampling
• Find hit in waveform
• Shift (“TDC”) and scale (“ADC”)
template to hit
• Minimize c2
• Compare fit with waveform
• Repeat if above threshold
• Store ADC & TDC values
Pile-up can be detected if two hits are
separated in time by ~rise time of signal
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Do we still need crates?
MEG 3000 channels
• An empty crate slot costs ~1k$
(crate, interface/computer, cooling)
• Crate topologies requires long cables
 Reduction of bandwidth
• Alternative: Put electronics on detectors
G. Varner
Belle-TOF
cPCI
GBit
Ethernet
H. Friedrich
WaveDREAM
PSI/ETHZ
Feb. 25th, 2010
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Experiments using SCA ASCIs
MEG 3000 channels
MAGIC-II
H.E.S.S.
ANTARES
Belle-TOF
Feb. 25th, 2010
ANITA
NSNI-2010 Mumbai
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Conclusions
• Fast waveform digitizing with SCA chips will
have a big impact on experiments in the
next future, replacing traditional ADCs
and TDCs
• SCA community growing! Exchange of
experience is important. Joining is easy
(e.g. USB evaluation boards)
• New generation of SCA chips on the horizon
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Thank You!
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