HV MOSFET Modeling with HiSIM_HV - MOS-AK

Report
Hiroshima University
HV MOSFET Modeling with HiSIM_HV
Benchmarks and New Developments
Ehrenfried Seebacher, Mitiko Muira Matausch, Kund Molnar
2011-09-16
Hiroshima University &
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HV Transistor
Compact Modeling Requirements
HV transistor sub-circuit modeling (the reference)
State of the art HV Transistor Compact Models
HiSIM_HV 1.x and 2.x
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Benchmarking: DC, AC
• Summary
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Presentation Overview
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RON (On Resistor) (high vgs, low vds, and temp.)
IDSAT (Saturation Current) ?
VT long & short
Cgg & Cgd Miller Cap
Analog parameter for long channel length
RF Parameter FT, FMAX ?
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FOMs for HV Transistor Modeling
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Nwell
PWELL
Increased junction breakdown voltage (BV)
of the drain diffusion is achieved
by using a deep drain well
Small on-resistance and high BV are contrary effects.
The optimization of the tradeoff between
both quantities is of major interest.
PWELL
NWELL
The gate length is extended beyond the body-drain
well junction, which increases the junction BV.
The gate acts as a field plate to bends the electric field.
RESURFeffect
Quasi-Saturation Effect.
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Nwell
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HV CMOS Transistor Types
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Sub-circuit Modeling
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HV MOS Transistor Model Features:
•Basic geometrical and process-related aspects
such as oxide thickness, junction depth, effective
channel length and width
•RON modeling
•Quasi saturation region and the saturation
region
•Geometry scaling, Short-channel effects
•1/f and thermal noise equation
•Temperature Modeling for RON, VT, IDSAT
•High Voltage Parasitic Models
•Bulk (Substrate) current
•Effects of doping profiles, substrate effect
•Modeling of weak, moderate and strong
inversion behavior
•Parasitic bipolar junction transistor (BJT).
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Model Limitations:
•RF modeling
•SH modeling
•Cgd, Cgg ……
•Graded channel
•Impact ionization in the drift region
•High-side switch (sub-circuit extension needed).
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Sub-circuit Model Features and Limitations
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EKV HV Transistor
–Under development within the EU Project COMON
“A Physics-Based Analytical Compact Model for the Drift Region of the HV-MOSFET” Antonios Bazigos, François Krummenacher, Jean-Michel
Sallese, Matthias Bucher, Ehrenfried Seebacher, Werner Posch, Kund Molnár, and Mingchun Tang
PSP HV – Transistor Model
–In development based on PSP surface potential model
MM20
–asymmetrical, surface-potential-based LDMOS model, developed by
NXP Research
HiSIM_HV
–CMC Standard model version 1.1.2 and 1.2.1
–Version 2.0.0 in evaluation
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State of the Art HV Compact Models and new Developments
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Complete Surface-Potential-Based Model
fS0 : at source edge
fSL : at the end of the gradual-channel approx.
fS(DL) : at drain edge (calculated from fSL)
Beyond Gradual-Channel Approximation
Channel-Length
Modulation
Overlap Capacitance
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Extension of Bulk-MOSFET Model HiSIM2
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a few hundred volts > Bias Range > a few volts
(Asymmetric)
Vgs,eff = Vgs – Ids x Rs
Vds,eff = Vds – Ids x (Rs + Rdrift )
Vbs,eff = Vbs – Ids x Rs
potential drop
(Symmetric)
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HiSIM-HV
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Consistent Modeling in Drift Region
Ldrift
Ndrift
Vds
Potential drop
in the drift region
V
Y. Oritsuki
et al., IEEE TED, 57, p. 2671, 2010.
DDP
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Y. Oritsuki et al., IEEE TED, 57, p. 2671, 2010.
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fS(DL)
VV
DDP
DDP
fS(DL) : potential determining
HV
LDMOS characteristics
Vgs [V]
HV
Vds [V]
HiSIM reproduces fS(DL) calculated by 2D-device simulator.
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fS(DL) [V]
fS(DL) [V]
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fS(DL) [V]
fS(DL) [V]
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Key Potential Values
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HiSIM_HV 1.0.0 Series
Bias Dependence is modeled based on principle.
Y. Oritsuki et al., IEEE TED, 57, p. 2671, 2010.
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Modeling of Rdrift
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Id [A]
Vgs=7.5V
Accuracy Comparison of Ids-Vds
: 2D-Device Simulation Results
: HiSIM-HV Results
Vgs=10V
Vgs=5V
Vgs=2.5V
Quasi-saturation behavior of LDMOS is reproduced.
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gd [S]
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Relatively Low Breakdown Voltage
Relatively High Breakdown Voltage
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Current-Voltage Characteristics
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Ids - Vgs
Gm vs. Vgs
Care must be taken when adjusting critical parameters describing the Vgs dependence.
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Empirical Model: Issues
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HiSIM_HV 1.1.2 v. BSIM3v3 Subcircuit
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Model Benchmark Output Characteristic
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Capacitance [fF]
2.0
0.8
Cgg
1.8
Cgd
1.2
Cgb
Vds=0V
-4
-2
Cgs
0.4
0
Vgs [V]
2
Normal MOSFET
Asymmetrical LDMOS
Symmetrical HVMOS
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Vgs [V]
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Capacitance [fF]
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Capacitance-Voltage Characteristics
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BSIM3+JFETS Subckt.
• Subcircuit: bad fitting quality, especially in accumulation.
• HiSIM_HV: good fitting quality in all regions.
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AC Modeling: Cgg
HiSIM_HV
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Self-Heating Effect for DC Analysis
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RC-Network:
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Self-Heating Effect for AC Analysis
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HiSIM_HV 2.0.0 Series
MOSFET + Resistor
DP
Channel
MOSFET
Resistor
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Modeling Rdrift
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Node potential Vddp is solved iteratively.
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VDDP
Velocity saturation affects strongly on I-V characteristics.
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Iddp
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I-V Characteristics of Resistor
2D-Device Simulation
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Lover
Wdep
Djunc Wjunc
I d d p  W  x o v  q  n   d rift 
W0
xdep
Vddp
L d rift
xov
xjunc
x ov  W 0
 W
W0
0
- A
W dep +
W ju n c
D
L o ve r
 ju n c
xdep
Iddp
Vddp
W0 
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Modeling Current-Flow in Overlap Region
L o ve r  D ju n c
2
xjunc
2
Djunc : junction depth
: current exude coefficient into
A
depletion region
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



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2D-Device Sim.
HiSIM_HV
Id [mA]
Vds = 0.5V, 2V, 5V, 10~30V
Id [mA]
Vgs [V]
Vgs= 3~9V, 15V, 30V
Vds [V]
xov improvements
The xov model
enables to fit I-V
characteristics
for wide range
of bias
conditions.
Vds = 0.5V, 2V, 5V, 10~30V
Vds = 0.5V, 2V, 5V, 10~30V
Vgs [V]
Id [mA]
Id [mA]
(Lch = 1m , Lover = 1m, Djunc = 2m)
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Verification of I-V Characteristics
Vgs= 3~9V, 15V, 30V
Vgs= 3~9V, 15V, 30V
Vds [V]
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HiSIM_HV 1.x.x Old Empirical
HiSIM_HV 2.x.x New Physical
Ids - Vgs
Gm vs. Vgs
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Empirical Model vs. Physical Model: IdVg
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HiSIM_HV 1.x.x Old Empirical
HiSIM_HV 2.x.x New Physical
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Empirical Model vs. Physical Model: IdVd
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HiSIM_HV Release
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HiSIM_HV 1.2.1 v. BSIM3 sub-circuit
HV NMOS output and transfer characteristic of a typical wafer. W/L=40/0.5,
VGS= 2.9, 4.8, 6.7, 8.6, 10.5, 12.4, 14.3, 16.2, 18.1, 20 V, VBS=0 V. &
VBS= 0, -1, -2, -3, -4 V, VDS=0.1 V.
+ = measured, full lines= BSIM3v3 model; dashed lines = HiSIM_HV 1.2.1
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The Extreme Case; 120V Transistors
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- HVMOS used on the low-side of a load:
Transfer Characteristics
Source and Substrate hold at the same potential
- HVMOS used on the high-side of a load:
Both Source and Drain can be placed at high potential
=> Ron is changing with Vsub-s
Vd=0.1V, Vs=Vb=0
HiSIM_HV 1.2.1: Vsub modulates the effective depth of the drift region: Rdrift(Vsub,s)
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Vsub=0
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Isolated HVMOS: High-Side Switch Modeling
Vsub=-120V
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HiSIM_HV
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The following effects are also included:
Complete Surface potential-based:
• Depletion effect of the gate polycrystalline
HiSIM_HV solves the Poisson equation along the MOSFET
silicon (poly-Si).
channel iteratively,
• Quantum mechanical
including the resistance effect in the drift region.
• CLM
• Narrow channel
high flexibility
• STI
20 model flags
• Leakage currents
scales with the gate width,
(gate, substrate and gate-induced drain
the gate length,
leakage (GIDL) currents).
the number of gate fingers
• Source/bulk and drain/bulk diode models.
and the drift region length.
• Noise models (1/f, thermal noise, induced
In addition, HiSIM_HV is capable of modeling
gate noise).
symmetric and asymmetric HV devices.
• Non-quasi static (NQS) model.
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Decision for HV Model depends very much on the application
Sub-circuit approach is very flexible and usable for switching
applications and for analog applications using large transistors
sizes.
HiSIM_HV 1.1.2 and 1.2.1 shows high accuracy for all benchmarks.
Detailed know how in parameter extraction needed
Extensive measurements necessary.
HiSIM_HV 2.x
First Version New physical drift region model is under evaluation
and shows excellent benchmark results.
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Summary
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