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EET 1131 Unit 4 Programmable Logic Devices Read Kleitz, Chapter 4. Homework #4 and Lab #4 due next week. Quiz next week. Programmable Logic Programmable Logic Devices (PLDs) are chips with a large number of gates that can be configured with software to perform a specific logic function. Major types of PLDs are: SPLD (Simple PLD): the earliest type of programmable logic, used for smaller circuits with a limited number of gates. CPLD (Complex PLD): contain multiple SPLD arrays and interconnection arrays on a single chip. FPGA (Field Programmable Gate Array): a more flexible arrangement than CPLDs, with much larger capacity. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Programmable Logic Advantages of PLDs over fixed-function chips include: Reduced complexity of circuit boards • Lower power requirements • Less board space • Simpler testing procedures Higher reliability Design flexibility © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Approximate Equivalent Densities The Lattice GAL22V10 (a popular SPLD) is equivalent to about 500 logic gates. A typical Altera MAX7000 CPLD is equivalent to about 2500 logic gates. A typical Altera Cyclone FPGA is equivalent to about 50,000 gates. Major PLD Manufacturers Three big names in this field are Xilinx, with 51% of market share Altera, with 34% Lattice, with less than 10% Market share numbers retrieved from Wikipedia on 9/10/2014. Some Product Lines from Altera and Xilinx Altera CPLDs: MAX FPGAs: Cyclone, Arria, Stratix Programming software: Quartus II Xilinx: CPLDs: CoolRunner, XC9500 FPGAs: Vertix, Spartan, Kintex, Artix Programming software: ISE PALs and GALs SPLDs contain arrays of gates. Two important kinds of SPLD are PALs (Programmable Array Logic) and GALs (Generic Array Logic). A typical array consists of a matrix of conductors connected in rows and columns to AND gates. PALs have a one-time programmable (OTP) array, in which fuses are permanently blown, creating the product terms in an AND array. A A B B X Simplified AND-OR array © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved PALs PALs are programmed with a specialized programmer that blows selected internal fuse links. After blowing the fuses, the array represents the Boolean logic expression for the desired circuit. A A B B What expression is represented by the array? X X = AB + AB © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved GALs The GAL (Generic Array Logic) is similar to a PAL but can be reprogrammed. For this reason, they are useful for new product development (prototyping) and for training purposes. A A B B GALs were developed by Lattice Semiconductor. X © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved PALs and GALs PALs and GALs are often represented by simplified diagrams in which a single line represents multiple gate inputs. The logic shown is for the same circuit shown earlier. Input buffer A A B B Single line with slash indicating multiple AND gate inputs Fuse blown X X 2 AB AB + AB Fuse intact X X 2 AB © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved GAL22V10 The GAL22V10 is a typical SPLD. It has 12 dedicated inputs pins and 10 pins that can be used as inputs or outputs. Link to datasheet © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved CPLDs A complex programmable logic device (CPLD) has multiple logic array blocks (LABs), each roughly equivalent to an SPLD. LABs are connected via a programmable interconnect array (PIA). Various CPLDs have different structures for these elements. The PIA is the interconnection between the LABs. I/O Logic array block (LAB) Logic array block (LAB) SPLD SPLD I/O PIA I/O I/O Logic array block (LAB) Logic array block (LAB) SPLD SPLD Logic array block (LAB) Logic array block (LAB) SPLD SPLD I/O I/O © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved FPGAs compared to CPLDs CPLDs Based on programmable AND array and fixed OR array. FPGAs Based on look-up table (LUT), which is basically a truth table. (Results in higher density.) Both are programmed using the same software, using either schematic entry or text entry. Programmable Logic Software All manufacturers of programmable logic provide software to support their products. The process is illustrated in the flowchart. The first step is to enter the logic design into a computer. It is done in one of two ways: 1) Schematic entry 2) Text entry using a hardware description language (HDL). Design entry Schematic HDL Synthesis Timing simulation Functional simulation Implementation Device programming (downloading) © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Programmable Logic Software Design entry Schematic HDL In schematic entry, the design is drawn on a computer screen by placing components and connecting then with simulated wires. After drawing the schematic, it can be reduced to a single block symbol: © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Programmable Logic Software Design entry Schematic HDL •In text entry, the design is entered via a hardware description language (HDL). •Learning an HDL takes longer than learning to do schematic entry. But for complex designs it can provide a more powerful and simpler way to enter designs. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Some Popular Hardware Description Languages Open-standard HDLs VHDL (IEEE 1076) Verilog (IEEE 1364) Proprietary HDLs CUPL ABEL (Advanced Boolean Expression Language, now owned by Xilinx) AHDL (Altera HDL) A VHDL Sample One way of writing VHDL programs is to use Boolean-type statements. There are two parts to such a program: the entity and the architecture. The entity portion describes the I/O. The architecture portion describes the logic. Following is a short VHDL program showing the two parts. entity Example is port (B,C,D: in bit; X: out bit); end entity Example; architecture Behavior of Example is begin X <= (B or C) and D; end architecture Behavior; Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Simulation Functional simulation After entering the circuit, the circuit is tested in a simulation. You can test the circuit with waveforms to verify the operation. The following shows the functional test of a counter using a waveform editor: © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Device Programming Device programming (downloading) The final step is to send the programming file from the computer to the target device and test the implementation. Shown is an Altera DE2-115 board with an Altera FPGA, along with switches, LEDs and many other I/O devices for testing your design after you’ve downloaded it to the FPGA. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Our Software and Equipment Software: Altera’s Quartus II, version 13.0 sp1. (Free download, so you can install it at home.) Hardware: Altera Cyclone IV FPGA. Chip is mounted on Altera’s DE2-115 experimenter’s board. (Manual on course website.) Three Ways of Representing a Digital Circuit We have at least three ways of describing a digital circuit: 1. 2. 3. Diagram showing the logic gates. Boolean expression. Truth table. Given any one of these, you should be able to write the other two. See examples on following slides. From Gate Diagram to Boolean Expression or Truth Table Given a gate diagram, you should be able to: 1. Write a Boolean expression for the diagram. 2. Write the truth table for the diagram. Example: Write a Boolean expression and the truth table for the following gate diagram. A B C X From Boolean Expression to Gate Diagram or Truth Table Given a Boolean expression, you should be able to: 1. Draw a gate diagram that implements the expression. 2. Write the truth table for the expression. In many cases your job will be easier if you first use Boolean algebra or a Karnaugh map to simplify the expression. We’ll study these techniques next week. Example: Draw a gate diagram and write the truth table for X = AB + ABC From Truth Table to Boolean Expression or Gate Diagram 1. 2. Given a truth table, you should be able to: Write a Boolean expression for that truth table. Here’s how: a) For each row in the truth table with a 1 in the output column, list the corresponding AND term of the input variables. b) OR together all of the AND terms from Step a. Draw a gate diagram that implements the truth table. Example: Write a Boolean expression and draw a gate diagram for the truth table on the next slide. Example: From Truth Table to Boolean Expression or Gate Diagram A B C X 0 0 0 0 0 1 0 1 0 0 0 1 0 1 1 1 1 1 1 0 0 1 0 1 0 0 1 0 1 1 1 0