lec16

```473 Quiz
• Assuming 4kB to save information about one function call,
what is the largest integer whose factorial can be calculated
by a recursive program whose address space is 4MB in size?
Ignore space occupied by code segment.
– factorial(n) = n ∗ factorial(n − 1), n > 1
– factorial(1) = 1
• ANSWER:
– The stack would only be able to hold 1,000 function frames. So the
largest integer would be 1,000.
• Which of the following is synchronous?
Interrupt arrival, Trap occurrence
• Answer:
– Synchronous: Generated at the end of an
instruction execution. Eg. Trap (Divide by zero,
system call using ‘int’ instruction)
– Interrupts are asynchronous – can arrive at
anytime (middle of a clock cycle – edge triggered
or level-triggered)
• Always handled at the end of the interrupted
instruction
• Assume a program with 1M instructions. Of these
40% refer to a data item or an instruction in
memory (load/store). Assuming one cycle per
instruction fetched to the CPU from memory and
ignoring hardware caches, how many cycles does
the program need to ﬁnish if there is no TLB?
• Answer:
– Load/store specify only virtual address and requires
virtual-physical address mapping to fetch from
memory (Hardware page table WALK)
– 1Million * 0.4 * 2 + 1Million* 0.6 = 1.4 Million
• Think of two ways a kernel could detect a
malfunctioning timer interrupt mechanism?
• Answer:
– Kernel uses timer interrupt as a means of time-keeping
– faulty timer interrupt can make the kernel think it is
running faster/slower
– First way: Run a piece of code with a predictable
relationship with the number of instructions it would
execute within a given amount of time. Then compare
this count with that expected based on the time
reported by the timer.
– Second way: Send messages to an external entity with
access to a functional timer and compare the time
elapsed between these with that reported by our
timer.
• We discussed the need to ﬂush the TLB upon
context switch on certain processors. What
would you change about the TLB for it not to
have to be ﬂushed upon a context switch?
• Answer:
– We would use what are called tagged TLBs, where
each translation entry within the TLB also has bits
to indicate which process (i.e., address space) that
entry corresponds to.
• What do you think happens when a data item
needed by a process is not found in main
memory?
• ANSWER:
– A trap is generated which causes the OS to run
and fetch these missing memory contents needed
by the process from a secondary storage device
(typically a disk) into main memory. This kind of
trap is called a page fault
• Recall user-level threads. Why is it safe to let a
user-level thread switch the CPU?
• Answer:
– It is safe to do so because of the notions of context
switching and virtual memory. A user-level piece of
code may ﬁll up the registers with any value (e.g.,
using something like setjmp), but the OS guarantees
that this will not affect the register contents seen by
any other process. A good example is the program
counter register. A process may ﬁll any address into
this register, but it would be a virtual address within
its own address space and would be safely translated
into a physical memory address assigned to this
process.
• Process scheduling is usually described as
selection from a queue of processes. For each
of these scheduling methods, describe the
selection method, the insertion method (if
required), further properties of the queue (if
required), and whether a simple queue should
be replaced by a more sophisticated data
structure.
• Answer:
– Round robin: Circular queue
– SJF: Heap or binary tree
– Multi-level feedback queue: queue of queues
• So far we have said that all registers including the
PC need to be saved when context switching out
a process. However, one can typically get away
without saving the PC (meaning it gets saved in
some other way). Where do you think it gets
saved? Who (what entity) saves it?
• Answer:
– Who saves PC register –hardware saves PC + stack
pointer in the kernel stack
• Which of process/K-level thread/U-level
thread would you pick to design an application
whose constituent activities: Are mostly CPUbound; Are mostly CPU-bound and need to
meet timeliness guarantees; Do a lot of
blocking I/O?
• Answer:
– IO bound: kernel-level threads since user-level
threads doing IO blocks the entire process
– CPU bound: User-level threads, context switching
overhead is small
• A process on an average runs for time T before
blocking for I/O. A context switch takes time S.
For round robin scheduling with quantum Q,
give a formula for CPU efﬁciency.
• Answer:
– CPU efficiency = time doing useful work/total time
– If Q=inf, efficiency = T/T+S
– If T=nQ, efficiency = nQ/(nQ+nS+S)
– If Q=nT, …
True or False
• (a) A process can send a signal to any other process.
(Answer: false)
• (b) The TLB must be ﬂushed when context switching
across user-level threads belonging to the same
process (i.e., address space). (Answer: false)
• (c) First-Come-First-Served (FCFS) is an appropriate
scheduler for a system with inter-active processes
(such as editors). (Answer: false)
• (d) Round robin is a non-work-conserving scheduler.
(Answer: false)
• (e) Traps are always synchronous. (Answer: true)
• (f) Condition variables and semaphores completely get
rid of busy waiting when used to construct entry
sections. (Answer: false)
• (g) Where does a global variable reside: (a) heap, (b) stack, (c)
code segment, (d) data segment? (Answer: data segment)
• (h) Which of these properties of a mutual exclusion solution,
if satisﬁed, automatically implies that the others are also
satisﬁed: (a) no starvation, (b) bounded wait, (c) no deadlock?
(Answer: bounded wait)
• (i) Upon a division by zero by a process, which kernel routine
of the following will get executed after switching to the kernel
mode: (a) an interrupt service routine, (b) a signal handler, (c)
a trap handler, (d) ﬂushing of certain kernel buffers? (Answer:
interrupt service routine)
• (j) Pick the CPU scheduling algorithm that provides the least
average waiting time among these: (a) First-Come-First-Served
(FCFS), (b) Shortest Job First (SJF), and (c) Round Robin (RR).
(Answer: shortest job first)
• Why is it safe in a multi-tasking system to let
user-level code write any address into the
Program Counter (PC) register?
• Answer:
– PC points to a virtual address – hence safe
• Can a piece of code remain atomic despite
being interrupted by the CPU scheduler? Why
or why not?
• Answer:
– yes, mutex locks can be used.
• Assume a Lottery scheduler and two
processes P1 and P2 with shares 1 and 2,
respectively. What is the probability that
process P2 will be chosen by the scheduler
successively 10 times?
• Answer:
– (2/3)10
• An OS uses round robin scheduling. A context
switch takes 0.002 msec while interrupt
handling takes 0.001 msec per interrupt. If the
quantum length is 10 msec and interrupts
arrive every 10 msec (at the middle of every
quantum), what is the CPU efﬁciency. CPU
efﬁciency is deﬁned as the ratio of useful CPU
time (used to run processes) to the total time.
• Answer:
– 10/(10+.003)
– (10 - .001)/(10+.002)
• In our discussion of signal handling, we saw
that after executing the signal handler
implemented by a process, there is a need to
go back to the kernel mode before resuming
the normal execution of the process.
• Answer:
– Where to return in user code?
• Thread A:
– statement a1
– statement a2
• Thread B:
– statement b1
– statement b2
• (i) a1 must happen before b2 and (ii) b1 must happen before a2. Both the
semaphores (bArrived and aArrived) are initialized to 0.
• Thread A:
–
–
–
–
statement a1
wait (bArrived);
signal (aArrived);
statement a2
• Thread B:
–
–
–
–
statement b1
wait (aArrived);
signal (bArrived);
statement b2
Can we use conditional wait
and signal ?
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