Basic MOS Device Physics

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Basic MOS Device Physics
Topics
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MOS Structure
MOS IV Characteristics
Second Order Effects
MOS Device Models
NMOS Structure
LD is caused by side diffusion
Substrate contact--to
reverse bias the pn junction
Connect to most negative supply voltage
in most circuits.
Source: the terminal that provides charge carriers.
(electrons in NMOS)
Drain: the terminal that collects charge carriers.
CMOS Structure
Connect to most positive
supply voltage in most circuits.
Reverse bias the pn
junction
NMOS
Reverse bias the pn
junction
PMOS
Symbols
This textbook
In Digital Circuits
MOS IV Characteristics
• Threshold Voltage
• Derivation of I/V Characteristics
– I-V curve
– Transconductance
– Resistance in the linear region
• Second Order Effect
– Body Effect
– Channel Length Modulation
– Subthreshold conduction
Threshold Voltage
1. Holes are expelled from the gate area
2. Depletion region (negative ions) is
created underneath the gate.
3. No current flows because no charge
carriers are available.
Threshold (2)
Two capacitors in series:
Cox: capacitance between the gate and oxide/silicon interface
Cdep: capacitance of the depletion region
As VG increases, the potential at the oxide/silicon increases.
Threshold Voltage (3)
When the surface potential increases to a
critical value, inversion occurs.
1. No further change in the width of the
depletion region is observed.
2. A thin layer of electrons in the depletion
region appear underneath the oxide.
3. A continuous n-type (hence the name
inversion) region is formed between the
source and the drain. Electrons can no
be sourced from S and be collected at
the drain terminal. (Current, however,
flows from drain to source)
4. Further increase in VG will fruther incrase
the charge density.
The voltage VG required to provide an
inversion layer is called the threshold voltage.
Body Effect
The n-type inversion layer connects the source to the drain.
The source terminal is connected to channel. Therefore,
A nonzero VSB introduces charges to the Cdep.
The math is shown in the next slide.
A nonzero VSB for NFET or VBS for PFET has the net effect
Of increasing the |VTH|
Math for Body Effect
Experimental Data of Body
Effect
W/L=12 um/0.12um
CMOS: 0.13 um process
VDS=50 mV
Simulator: 433 mV
Alternative method: 376 mV
Subthreshold current
Subtreshold
region
As VG increases, the surface
potential will increase.
There is very little majority carriers
underneath the gate.
There are two pn junctions. (B-S and B-D)
The density of the minority carrier
depends on the difference in the
voltage across the two pn junction diode.
A diffusion current will result the electron densities
Threshold Voltage
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VG=0.6 V
VD=1.2 V
CMOS: 0.13 um
W/L=12um/0.12 um
NFET
Implantation of p+ dopants to
alter the threshold
Threshold voltage can be adjusted by implanting
Dopants into the channel area during fabrication.
E.g. Implant p+ material to increase threshold voltage.
Formation of Inversion Layer in a
PFET
The VGS must be sufficient
negative to produce an inversion
layer underneath the gate.
I-V Characteristics
Channel Charge
A channel is formed when VG is increased to the point
that the voltage difference between the gate and
the channel exceeds VTH.
MOSFET as a variable resistor
The conductive channel between S and D can be viewed
as resistor, which is voltage dependent.
Application of VDS
What happens when you introduce a voltage at the drain terminal?
Channel Potential Variation
E.g. VS=0, VG=0.6, VD=0.6
At x=0, VG-VX=0.6 (more than VTH)
At x=L, VG-VX=0 (less than VTH)
VX the voltage along the channel
VX increases as you move from S to D.
VG-VX is reduced as you
move from S to D.
Pinch Off
Linear
Region
Small VDS
Saturation
Region
Large VDS
No channel
Electrons reaches the D
via the electric field in the
depletion region
Conceptual Visualization of
Saturation and Triode(Linear)
Region
NMOS
PMOS
I-V Characteristic Equations for
NMOS transistor
To produce a channel (VGS>VTH)
(Triode Region:
VDS<VGS-VTH)
Saturation: VDS>VGS-VTH
I-V characteristic Equation for
PMOS transistor
MOSFTE as a controlled linear
resistor
1. Take derivative of ID with respect to VDS
2.
For small VDS, the drain resistance is
Example
Ron=233.625 Ohms
VS=100/(100+233.625)
*100 mV=29.97 mV
Sweep VGS to change MOS
resistance and VS
Transistor in Saturation Region
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I-V characteristics
Transconductance
Output resistance
Body transconductance
Saturation of Drain Current
Transconductance
Analog applications:
How does ids respond to changes in VGS?
IDS vs VGS
0.13 um NMOS
VDS=0.6 V
W/L=12um/0.12 um
VB=VS=0
Y axis: ids
X axis: Vgs
Different Expressions of
Transconductance
Transconductance in the triode
region
(Triode region)
For amplifier applications, MOSFETs are biased in saturation
gm as function of region
0.13 um NMOS
VGS=0.6 V
W/L=12um/0.12 um
VB=VS=0
Y axis: gm
X axis: vds
saturation
linear
Channel Length Modulation
As VDS increases, L1 will move towards the source, since
a larger VDS will increase VX .
L is really L1
ID will increase as VDS increases.
The modulation of L due to VDS is called channel length modulation.
Controlling channel modulation
For a longer channel length, the relative change in L and
Hence ID for a given change in VDS is smaller.
Therefore, to minimize channel length modulation, minimum
length transistors should be avoided.
gds
0.13 um NMOS
VGS=0.6 V
W/L=12um/0.12 um
VB=VS=0
Y axis: gm
X axis: vds
Slope due to
channel length
modulation
saturation
linear
Output resistance due to gds
More on Body Effect
• Example
• Analysis
• gmbs
Variable S-B Voltage
constant
VTH as a function of VSB
Body effect coefficient
VSB dependent
(VTH0: with out body effect)
Sensitivity of IDS to VSB
gm
(chain rule)
η=1/3 to 1/4, bias dependent
Small Signal Model
• If the bias current and voltages of a
MOSFET are only disturbed slightly by
signals, the nonlinear amd large signal
model an be reduced to linear and
small signal representation.
Small signal model of an NMOS
MOS Device Layout
MOS Capacitances
Bias dependent CGS and CGD
Complete NMOS Small Signal
Model
Complete PMOS Small Signal
Model

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