### Power dividers and couplers part 1x

```ECE 5317-6351
Microwave Engineering
Fall 2011
Prof. David R. Jackson
Dept. of ECE
Notes 19
Power Dividers and Couplers
Part 1
1
Power Dividers and Directional Couplers
Three-port networks
P1
P2   P1
Divider
P3  1    P1
P1  P2  P3
Coupler
(Combiner)
P2
P3
General 3-port:
 S 11

 S    S 21
S
 31
S 12
S 22
S 32
S 13 

S 23

S 33 
2
Power Dividers and Directional Couplers (cont.)
For all ports matched, reciprocal, and lossless:
 0

  S   S 12

S
 13
S 12
0
S 23
S 13 

S 23

0 
Not physically possible
(There are three distinct values.)
Lossless  [S] is unitary
 S 12
S 12
S 13
2
 S 13
2
1
2
 S 23
2
1
 S 23
2
2
1
These cannot all be satisfied.
(If only one is nonzero, we cannot satisfy all three.)

S 13 S 23  0

S 12 S 23  0
S

12
S 13  0
 At least 2 of S13, S12, S23 must be zero.
(If only one is zero (or none is zero), we cannot satisfy all three.)
3
Power Dividers and Directional Couplers (cont.)
Now consider a 3-port network that is non-reciprocal, all ports matched, and
lossless:
 0

  S   S 21

S
 31
S 13 

S 23

0 
S 12
0
S 32
“Circulator”
These equations will be satisfied if:
(There are six distinct values.)
Lossless
 S 21
S 12
S 13
2
2
2
 S 31
2
1
 S 32
2
1
 S 23
2
1

S 31 S 32  0

S 21 S 23  0
1
S12  S 23  S 31  0
S 21  S 32  S13  1
2
or
Note that Sij  Sji.
S 21  S 32  S13  0
S12  S 23  S 31  1

S 12 S 13  0
4
Circulators
Clockwise (LH) circulator
1
0

S    1
0

0
0
1
S 21
1

0

0 
2
S32
1
Note: We have assumed here that the phases
of all the S parameters are zero.
2
0

S    0
1

1
0
0
0

1

0 
biased ferrite materials.
S13
3
S 12
2
S 23
1
S31
3
Counter clockwise (RH) circulator
5
Power Dividers
T-Junction: lossless divider
Yin1
Z 02
Z 01
Yi n1 
1

Z 02
1
Yin3
Z 03
T o m a t ch  Yi n1 
1
Z 01
N o te , h o w e v e r, Yin3 
T h u s , Yin3 
1
Z 03
 Z 01  Z 02 | | Z 03 
1
Z 01

1

Z 02
A ls o , Yin 2 
Z 02  Z 03
Z 02 Z 03
Z 03
Z 02 Z 03
Z 02  Z 03

1
Z 02

Z 02  2 Z 03
Z 02 Z 03

1  Z 02  2 Z 03 


Z 03 
Z 02

1
Z 02
If we match at port 1, we cannot
match at the other ports!
6
Power Dividers (cont.)
Assuming port 1 matched:
Z 01 
Z 02 Z 03
2
Z 02  Z 03
Z 02

1
Pin1 
1 V1
Pout 2 
Pou t3 
Z 01
V1

2
Z 03
2 Z 01
1 V1
2

2 Z 02
1 V1
Z 01
Z 02
2
2 Z 03

Z 01
Z 03
Pin1
3


Z 03

 Pi n1  K Pin1
 Z 02  Z 0 3 


Z 02
Pi n1  
 Pi n1   1  K  Pi n1
 Z 02  Z 03 
We can design the splitter to control the powers into the two output lines.
7
Power Dividers (cont.)
For each port we have:
S11 

V1
V1
Z 02
Z 01


Z 03
a2  a3  0
Z 02 Z 03  Z 01
Z 02 Z 03  Z 01
 ze ro if p o rt 1 is m a tc h e d 

S 22 

V2
V
+ +
V1 V2
- -

2 a a 0
1
3
Z 01 Z 03  Z 02
Z 01 Z 03  Z 02

S 33 

V3

V3
a1  a 2  0
Z 01 Z 02  Z 03
Z 01 Z 02  Z 03
8
Power Dividers (cont.)
Also, we have
Z 02

V2
S 21 

Z 01
V1  V1
Z 01
Z 02
V1

+ +
V1 V2
- Z 03
a 2  a3  0
1  S 11 

; V 2  V 2  V1
 S 21   1  S 11 
Z 01
Z 02




V 2 / V1  V1 / V1  1  S 11
 S 12
S im ila rly,
S 31  S 13   1  S 11 
Z 01
Z 03
a n d S 32  S 23   1  S 22 
Z 02
Z 03
9
Power Dividers (cont.)
If port 1 is matched:
 S 11  0 ;
S 22 
S 21  S 12   1  S 11 
S 13  S 31   1  S 11 
S 32  S 23   1  S 22 
Z 01 Z 03  Z 02
Z 01 Z 03  Z 02
Z 01

Z 02
Z 01
Z 01
Z 01 
Z 01


Z 03
Z 03
Z 02
  1  S 22 
Z 03
Z 02  Z 03
; S 33 
Z 02

Z 02 Z 03
Z 01 Z 02  Z 03
Z 01 Z 02  Z 03
Z 03
Z 02  Z 03
Z 02
Z 02  Z 03
Z 02
 0

 S    S 21
S
 31
S 21
S 22
S 32
S 31 

S 32

S 33 
Z 03
The output ports are not isolated.
10
Power Dividers (cont.)
Powers:
P2
P1
P3
P1
 S 21
2
 S 31
2
Hence
P3
P2


Z 03


Z

Z
03 
 02


Z 02


Z

Z
03 
 02

Z 02
Z 03




Z 03
Z 02
C h e ck : P1  P2  P3  
P

 1 
 P1  P1
 Z 02  Z 0 3 
 Z 0 2  Z 03 
11
Power Dividers (cont.)
Summary
Z 01 
2
Z 02
Z 02 Z 03
Z 02  Z 03
1
P3
Z 01
P2
Z 03
S 11  0 ;
S 21  S 12 
S 13  S 31 
S 22 
Z 01 Z 03  Z 02
Z 01 Z 03  Z 02
Z 02
Z 03
3
Z 01 Z 02  Z 03
Z 01 Z 02  Z 03
 The input port is matched,
but not the output ports.
Z 03
Z 02  Z 03
 The output ports are not
isolated.
Z 02
Z 02  Z 03
S 32  S 23   1  S 22 
; S 33 

Z 02
Z 03
12
Power Dividers (cont.)
Example: Microstrip T-junction power divider
S11  0
Z 02  100 [  ]
S 22  S 33  
1
2
Z 01  50 [  ]
Z 0 1 Z 0 2  Z 0 1 Z 0 3  5 0 1 0 0  3 3 .3 3 3 [  ]
S 21  S12 
1
S 31  S13 
1
S 32  S 23 
2
2
Z 03  100 [  ]
1
2
13
Resistive Power Divider
Z0
Z in 1 
Z0
3
3

Z0
2Z0
3


Z in1
4Z0 4Z0
3
Z0
3
3
 Z0
Z0

V1

port1
Same for Zin1 and Zin2
Z0
3
V
2
port2
Z0
3 
V3
port3
Z0
 All ports are matched.
S 11  S 22  S 33  0
14
Resistive Power Divider (cont.)

V2
S 21 
V1

V2

Z in1

Z0
V1  V1
Z0
Z0
a2  a3  0
Z0
 1  S 11   V1
2

Z0

3
 V 2  V1 
Z
2
 0  Z0
3
 3
 V1
Z0
3



Z0
 Z
 0  Z0
 3





 2  3  1 
     V1
 3  4  2
 S 21 
1
2

V1

port1
Z0
3
V
2
port2
Z0
3 
V3
port3
Z0
By reciprocity and symmetry
 S 12  S 3 1  S 13  S 32  S 23
15
Resistive Power Divider (cont.)
P2
Hence we have
Z in1
Z0
3
P1
0
1
S

1
 

2
1
1

1

0 
1
0
1

V1

Z0
port1
P1  Pin 
P2  P3 

1
2 Z0
2
1
1
2
b2
2

2
V
2
port2
Z0
3 
V3
port3
2
1 V1
Z0
3
a1
2
a1 S 21
2
 P1 S 21
2
 P1
1
2
2

Z0
P3
Z0
Pin
4
All ports are matched, but 1/2 Pin is dissipated by resistors, and the
output ports are not isolated.
16
Even-Odd Mode Analysis
(This is needed for analyzing the Wilkenson.)
Obviously,
Example: We want to solve for V.
Let V
e
S
V
o
S

1
2
2 
VS
VS
using even/odd mode analysis
POS
2 

e
S
V
Ve
2 
2 

“even” problem
Plane of symmetry
e
S
V

V


V V V
e
2 
2 
POS
2 
 1  VS
V  VS 

2

1
3


2 

VSo
V0
2 
VSo

o
“odd” problem
17
Even-Odd Mode Analysis (cont.)
“Even” problem
POS
POS
2 
V
V

I 0
2 


e
S
2 
2 
e
2 
VS
2
VSe
4 
Ve

4 
VS
2
Open circuit (OC)
plane of symmetry
2 

VS
2
4 
Ve

V
e
VS  4  VS



2 24
3
18
Even-Odd Mode Analysis (cont.)
“Odd” problem
POS
2 
POS
2 
2 


o
S
V
Vo
2 
VS
2
VSo

2 
VS
2
2 
4 
4 
Vo 0

4 
VS
2
short circuit (SC)
plane of symmetry

Vo
V
o
0

19
Even-Odd Mode Analysis (cont.)
2 

V

VS
2 
2 
2 
2 

VS
2
2 
Ve

2 


VS
2
2 
VS
2
Vo

2 
VS
2
“odd” problem
“even” problem
By superposition: V  V e  V
o

VS
0
3
 V 
VS
3
20
Wilkenson Power Divider
Equal-split (3 dB) power divider
2
Z0
Z0
0
2Z
g
/4
1
2Z 0
2Z
0
 All ports matched (S11 = S22 = S33 = 0)
g
Z0
3
/4
 Output ports are isolated (S23 = S32 = 0)
Note: No power is lost in going
from port 1 to ports 2 and 3.
S 21
2
 S 31
2

1
2
0
j 
1
S  

2 
1
1
0
0
1

0

0 
Obviously not unitary
21
Wilkenson Power Divider (cont.)
Example: Microstrip Wilkenson power divider
Z 02  50 [  ]
Z 0 T  70.7 [  ]
R  100 [  ]
Z 01  50 [  ]
Z 0 T  70.7 [  ]
Z 03  50 [  ]
22
Wilkenson Power Divider (cont.)
• Even and odd analysis is required to analyze structure
when port 2 is excited.

To determine
S 22 , S 32
• Only even analysis is needed to analyze structure
when port 1 is excited.

To determine
S 11 , S 21
The other components can be found by using symmetry and reciprocity.
23
Wilkenson Power Divider (cont.)
Top view
Z0
V2
V2
Z
0
2
V
V

/4
g

1

1
Z0
g
2Z
0
A microstrip realization is shown.
/4
2Z 0
Plane of
symmetry
Z0
V3
V3
Split structure along plane of symmetry (POS)
Even  voltage even about POS  place OC along POS
Odd  voltage odd about POS  place SC along POS
24
Wilkenson Power Divider (cont.)
g
V2
V2
2
Z
0
V1
V1
Z0
/4
g
Z0
2Z
/4
2Z 0
Plane of
symmetry
Z0
0
V3
V3
How do you split a transmission line? (This is needed for the even case.)
top view
Z0
I /2
POS
Voltage is the same for each half of line (V)
Current is halved for each half of line (I/2)
I /2
(magnetic wall)
Z0 microstrip line
 Z0 
h
For each half
V
I 2
 2Z0
25
Wilkenson Power Divider (cont.)
“Even” Problem
V2e

/4
V
V e
Z0
2Z
0
g
Z0
Note: The 2Z0 resistor has
been split into two Z0
resistors in series.
2Z 0
V1e
OC
Ports 2 and 3 are excited in phase.
V1e
OC
2Z
0
2Z 0
g
/4
Z0
V
Z0
V3e
V e
N o te : V 3  V 2
e
e
26
Wilkenson Power Divider (cont.)
“Odd” problem
V2o
2Z
g
/4
2Z 0
0
V
Z0

Note: The 2Z0 resistor has
been split into two Z0
resistors in series.
V o
Z0
V1o
Ports 2 and 3 are excited 180o out of phase.
V1o
2Z
0
2Z 0
g
/4
N o te : V1  0,
o
Z0
V3o
V 
Z0
V  o
V 3  V 2
o
o
27
Wilkenson Power Divider (cont.)
Z ine 2 , S22e
Even Problem
V2e
Port 2 excitation
g

/4
e
in 2

 S
e
22
Z

2 Z0
2Z0

V1e
V
Port 2
V e
2
2Z 0
Z0
Z0
OC
2
 Z0
Z in 2  Z 0
e

Z
e
in 2
 Z0
 0
A lso, by sym m etry, S 33  0
e
28
Wilkenson Power Divider (cont.)
o
Z ino 2 , S22
Odd Problem
V2o
Port 2 excitation
g
Z0

/4
0
2Z
Z0
V
V
o
Port 2
V1o
2Z 0
short
V1  0
o
Z in 2   Z 0  Z 0
o
Z in 2  Z 0
o
 S
o
22

Z
o
in 2
 Z0
 0
A ls o , b y s ym m e try, S 3 3  0
o
29
Wilkenson Power Divider (cont.)
We add the results from the even and odd cases together:

S 22 
V2
V

2 a a 0
1
3
S 22 
V
e
V

V V
o


V

S 32 
V

2 a a 0
1
3
S 32 
V
e

V
V V

o


1
2
1
 S 22  S 22  
e
o
2
0  0
 0
S 33  0 (by sym m etry)
o

Note: Since all ports have
the same Z0, we ignore the
normalizing factor Z0 in
the S parameter definition.
V
2V

V3
e

V
e
V
2V
o


1
2
 S 22  S 22  
e
o
1
2
0  0  0
S 2 3  0 (by reciprocity)
In summary,
S 22  0
S 33  0
S 32  S 23  0
30
Wilkenson Power Divider (cont.)
Z0
Port 1
Z0
V2
0
g
Z
V1
V1
2
Port 1 excitation
/4
g
2Z 0
/4
Z0
2Z
0
V3
When port 1 is excited, the response, by symmetry, is even.
(Hence, the total fields are the same as the even fields.)
Even Problem
V
V
Z0
g
2Z
2Z 0
Z0
g
Z0
/4
0
2
Z
0
V
V

1

1
2 Z0
2Z
g

1

1
Z0
/4
O.C.
symmetry
plane
OC
0
/4
31
Wilkenson Power Divider (cont.)
2
Even Problem
e
1 e
V
V1
Port 1 excitation
Z
e
in 1


2Z0

2Z 0
2
 2Z0
Z0
Z in 1  2 Z 0
g
Z0
/4
0
Z
2
1
Z ine 1 , S11e
OC
e
S 11 
e
Z
e
in 1
 2Z0
0
Hence
S 11  0
S 11 
V1
V1



a2  a3  0
V1
V1
e
 S 11  0
e
e
a2  0
32
Wilkenson Power Divider (cont.)

Even Problem
V1
V1
V1  V1

V1

a 2  a3  0
2Z 0
V2
OC
Along g/4 wave transformer:
1  S 11   V1

z
0
S 21 
Port 1 excitation
/4
2Z

V2
g
Z0

V2  V2  V2
V  z   V0 e

 j z
1   e
 j2 z

z  d is ta n c e fro m p o rt 2

 S 21 

V2
V1


S 21 
V2
V1
j
2

1   
j
1   
j
2
2 2
V 2  V  0   V 0 1   

V1  V    g / 4   V 0 j  1   

 S 12
(reciprocal)
 
Z0 
2Z0
Z0 
2Z0

1
2
1
2
33
Wilkenson Power Divider (cont.)
For the other components:
By symmetry:
S 31  S 21 
j
By reciprocity: S 13  S 31   j
2
2
34
Wilkenson Power Divider (cont.)
0
j 
1
S  

2 
1
1
0
0
1

0

0 
Z0
/4
S 11  S 22  S 33  0
2
Z
0

g
Z0
g
2Z
0
/4
2Z 0
Z0
S 32  S 23  0
All three ports are matched, and the output ports are isolated.
35
Wilkenson Power Divider (cont.)
0
j 
S

1
 

2 
1
1
0
0
1

0

0 
Z0
/4
S 21  S 31 
0
2
Z
g
Z0
g
2Z
0
/4
2Z 0
Z0
S12  S13 
j
2
j
2
 When a wave is incident from port 1, half of the total incident power gets transmitted
to each output port (no loss of power).
 When a wave is incident from port 2 or port 3, half of the power gets transmitted to
port 1 and half gets absorbed by the resistor, but nothing gets through to the other
output port.
36
Wilkenson Power Divider (cont.)
Figure 7.15 of Pozar
Photograph of a four-way corporate
power divider network using three
microstrip Wilkinson power dividers.
Note the isolation chip resistors.
Courtesy of M.D. Abouzahra, MIT Lincoln Laboratory.
37
```