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Energy Efficiency, Arithmetics and Design Effort on FPGAs Case study: Reconfigurable Miniature Sensor Nodes for Condition Monitoring Teemu Nyländen, Jani Boutellier, Karri Nikunen, Jari Hannuksela, Olli Silvén Introduction • WSNs for condition monitoring – – – – Wide range of algorithms with very different processing needs Need to adapt to prevailing energy conditions Cheap and low power Fixed design out of question • Floating point vs Fixed point – Typically fixed point preferred in embedded designs – Floating point designs do not necessarily carry energy efficiency penalty – The design time and effort speaks for floating point designs • FPGAs vs ASICs — ASICs usually targeted to a larger spectrum of users and applications — FPGA based implementations can be made more specific Our TTA mote Flash FPGAs help to avoid overprovisioning and provide for energy efficient implementations that rival off-the-shelf SoCs for sensor node designs Floating point implementations rival fixed point designs Transport triggered architecture (TTA) is an attractive framework for designs Instruction level parallelism at low programmability overheads Why wireless? • Wouldn’t it be much easier to use wired solutions? – Connections break easily – Maintenance a major expenditure – Wired solutions cannot be used everywhere – Wireless is simply easier, cheaper and enables condition monitoring in places formerly impossible http://www.hub-4.com/news/s1/5000/compactonline-sensor-monitors-condition-of-vibratingscreens-pumps-and-motors Why energy autonomous? • There is plenty of energy available in the industrial environment. Why do you need energy harvesting? – Energy harvesting enables wireless solutions – Batteries cannot always be replaced – Currently battery/super condensator needed http://vibpower.w3.kanazawa-u.ac.jp/about-e.html Why not just use off-theshelf WSN solutions or ASICs? • Off-the-shelf solutions are often compromises – Target as wide spectrum of users as possible – Low power consumption – Low power consumption but poor performance or vice versa • ASICs – Very low power, very energy effiecient – Long design and testing times – Fixed Flash vs SRAM FPGA Altera Cyclone III + Embedded multipliers + Unlimited reprogrammability + Logic element composition (4LUT) - Higher static and therefore total power consumption Actel Igloo + Designed for energy efficiency + Very low static power consumption - Limited reprogrammability - Logic element composition (3LUT) - No embedded multipliers - 130 nm technology Power dissipation ARITHMETIC CORE VOLTAGE (V) Clock (MHz) TOTAL POWER DISSIPATION (mW) DYNAMIC POWER DISSIPATION (mW) 32-bit Floating point 1.2 11 59.41 7.45 32-bit Floating point 1.2 45 72.77 20.81 32-bit Fixed point 1.2 15 59.78 7.82 32-bit Fixed point 1.2 60 78.18 26.22 32-bit Floating point CORE VOLTAGE (V) 1.2 Clock (MHz) 11 TOTAL POWER DISSIPATION (mW) 8.96 DYNAMIC POWER DISSIPATION (mW) 8.90 32-bit Floating point 1.5 20 25.22 25.01 32-bit Fixed point 1.2 15 12.61 12.55 32-bit Fixed point 1.5 30 40.42 40.20 16-bit Floating point 1.2 15 6.74 6.68 16-bit Floating point 1.5 30 21.78 21.56 16-bit Fixed point 1.2 15 7.01 6.96 16-bit Fixed point 1.5 30 21.87 21.65 ARITHMETIC Our TTA mote • 32-bit,16-bit floating point and 16-bit fixed point More about TTAs: http://tce.cs.tut.fi Bearing fault monitoring • Time and frequency based analysis – Time: RMS, Kurtosis,... – Frequency: Spectrum analysis • Processing needs vary greatly • Analysis based on the energy state Floating point vs Fixed point Arithmetic Silicon Area (Actel Versatiles) Power Dissipation (mW) Notes 16-bit FXP 800 0.064 Unnormalized 16-bit FLP 1350 0.164 Incl. normalization Floating point vs Fixed point Arithmetic Power Dissipation (mW) Energy Consumption 256-FFT (uJ) Throughput (FFT/mJ) 16-bit FLP 20.084 75.36 14.6 16-bit FXP 20.688 94.74 12.9 TTA mote vs off-the-shelf solutions Platform Maximum Clock Rate (MHz) Total power dissipation (mW) MICAz 4 33 TelosB 8 3 Proposed TTA 16-bit FLP 20 4.179 @ 4 MHz Proposed TTA 16-bit FLP 20 8.303 @ 8 MHz TTA mote vs TelosB Platform Total Energy Consumption uJ @ 4.1 MHz Maximum Clock Rate (MHz) TelosB 64-FFT FXP 119.6 8 TelosB 256-FFT FXP 604.2 8 Proposed TTA 64-FFT FLP 14.87 20 Proposed TTA 256-FFT FLP 68.28 20 THANK YOU!