ASIC Implementation for `Internet of Everything` devices

Implementation for
‘Internet of
Everything’ devices
Dec 2012
Requirements – energy budget
Requirements – energy consumed
Balance - energy consumed against budget
Implementation challenges
Implementation techniques
Power Requirements
 Interconnected devices can help make residential and commercial building
more energy efficient.
 In order to have overall energy reduction, the collection of interconnected
devices must themselves be very energy efficient.
 For Line powered devices < 1 mW average power is good enough.
 For battery powered device, the battery replacement interval must be
 The most common low cost batteries are alkaline AAA and AA, and coin cell.
 Two AAA batteries contains 7500 Joules of useable energy. In order to last 2 years,
average power must be below 120uW.
 A CR2450 coin cell battery contains 4300 Joules useable energy. In order to last 2
years, average power must be below 70uW.
Interconnected device Capabilities
Energy Implication
Application specific energy per discrete sensing event.
Each sensing event could consume 100uW to 10 mW of
Local Processing
• Filtering raw sensor data
• Comparing to thresholds, triggering
• Packaging for transmit or storage
CPUs and associated memories typically burn 5 mW of
energy. Devices need to start processing quickly, and turn off
CPU subsystem as soon as possible.
• Typically Internet cloud connected
for simplified configuration and
ecosystem integration
• Typically wireless for simplified
Internet connected CPU subsystem require more code space,
and ram which contributes to energy leakage.
Wireless systems need more energy in phy layer to establish
Typically 200mW – 750mW needed to support com link
Environment Control
• Display or indicator
• Actuator
Displays can burn from 30uW to 500mW of energy.
Motors can take significantly more energy.
Efficient Activation
 Major tasks consume much more energy than target power level.
 Typically, while tasks are running power is 300mW.
 Duty cycling to a lower standby current is critical to achieving lower
 Standby power with state retention bring power level down to 30uW
Duty Cycle
(Standby to Active)
Average Power
3,000 uW
330 uW
33 uW
 Duty cycle of 10,000 : 1 corresponds to 6 ms of activity every 1 minute
 Device to cloud centric use cases are simpler, transmit can be asynchronous.
 Cloud to device centric use cases have latency and availability implications
with this duty cycling.
 Device can poll for data
 Device can be synchronized with network and listen of data at specific intervals
Challenges for Silicon Implementation
 Market demands lower cost of smaller process nodes, but this drives leakage
currents higher.
 Higher level of integration is required in these small interconnected devices,
which requires combining RF process with logic process and non volatile
memory processes.
 For some sensing and control applications, higher voltages (12 V) are also
 Requirement for TCP/IP cloud connectivity increases memory footprint and
non-volatile storage requirements which increases leakage.
Low Power Silicon Implementation Strategies
Total Power Reduction
Efficient Activity Scheduling
Static power / Leakage reduction Techniques
Dynamic power reduction techniques
High VT / Multi VT logic library
Course Clock Gating
Ultra High Density logic library
Fine Grain Clock Gating
Course grain Power Islands
Dynamic Frequency Scaling
Fine grain power gating
Retention Flip flops
Voltage Scaling
Low Leakage SRAM
Asynchronous Logic
Voltage Scaling for SRAM while in suspend state
NV Memory for code storage
NV memory for data storage
Low power oscillators or MEM Resonators
Back Bias Logic
Back Bias Logic
Advancements in Communication ASIC
efficiency and silicon implementation
 Duty cycling advancements
 protocols such as 802.11 are adding support for connected devices in longer duration
standby state.
 low latency startup and fast return to suspend state
 Active power advancements
 900 MHz band enables longer range and lower power receive and transmit.
 Standby power advancements
 multiple power islands, with separate high efficient regulator for always on circuits.
 Segregated RAM with separate power collapse regions and non volatile regions
 fine grain power gating to minimize leakage from logic in standby state

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