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數位系統 Digital Systems Department of Computer Science and Information Engineering, Chaoyang University of Technology 朝陽科技大學資工系 Speaker: Fuw-Yi Yang 楊伏夷 伏夷非征番, 道德經 察政章(Chapter 58) 伏者潛藏也 道紀章(Chapter 14) 道無形象, 視之不可見者曰夷 Fuw-Yi Yang 1 Text Book: Digital Design 4th Ed. Chapter 7 Problems 7.4 Show the memory cycle timing waveforms for the write and read operations. Assume a CPU clock of 100 MHz and a memory cycle time of 25 ns. Fuw-Yi Yang 2 Text Book: Digital Design 4th Ed. Chapter 7 Problems 7.4 Show the memory cycle timing waveforms for the write and read operations. Assume a CPU clock of 100 MHz and a memory cycle time of 25 ns. Fuw-Yi Yang 3 Text Book: Digital Design 4th Ed. Chapter 7 Problems 7.6 Enclose the 4 X 4 RAM of Fig. 7.6 in a block diagram showing all inputs and outputs. Assuming three-state outputs, construct an 8 X 8 memory using four 4 X 4 RAM units. Fuw-Yi Yang 4 Text Book: Digital Design 4th Ed. Chapter 7 Problems 7.6 Enclose the 4 X 4 RAM of Fig. 7.6 in a block diagram showing all inputs and outputs. Assuming three-state outputs, construct an 8 X 8 memory using four 4 X 4 RAM units. Fuw-Yi Yang 5 Text Book: Digital Design 4th Ed. Chapter 7 Problems 7.7 A 16K X 4 memory uses coincident decoding by splitting the internal decoder into X-selection and Y-selection. a. What is the size of each decoder, and how many AND gates are required for decoding the addresses? b. Determine the X and Y selection lines that are enabled when the input address is the binary equivalent of 6,000. Fuw-Yi Yang 6 Text Book: Digital Design 4th Ed. Chapter 7 Problems a. What is the size of each decoder, and how many AND gates are required for decoding the addresses? 16K = 27 * 27 Required gates: 2 * 128 = 256 AND gates, each with 7 inputs leads cost = 256 * (7 + 1) = 2048 units For one dimensional decoding Required gates: 16384 AND gates, each with 8 inputs leads cost = 16384 * (8 + 1) = 147456 units b. Determine the X and Y selection lines that are enabled when the input address is the binary equivalent of 6,000. 600010 = 0101110 11100002 Fuw-Yi Yang 7 Text Book: Digital Design 4th Ed. Chapter 7 Problems 7.8 a. How many 32K X 8 RAM chips are needed to provide a memory capacity of 256K bytes? b. How many lines of the address must be used to access 256K bytes? How many of these lines are connected to the address inputs of all chips? c. How many lines must be decoded for the chips select inputs? Specify the size of the decoder? Fuw-Yi Yang 8 Text Book: Digital Design 4th Ed. Chapter 7 Problems a. How many 32K X 8 RAM chips are needed to provide a memory capacity of 256K bytes? 8 chips b. How many lines of the address must be used to access 256K bytes? How many of these lines are connected to the address inputs of all chips? using 18 address lines to address 256K memory unit using 15 address lines to address 32K memory unit c. How many lines must be decoded for the chips select inputs? Specify the size of the decoder? 3 address lines as inputs to a 3 X 8 decoder Fuw-Yi Yang 9 Text Book: Digital Design 4th Ed. Chapter 7 Problems Fuw-Yi Yang 10 Text Book: Digital Design 4th Ed. Chapter 7 Problems a. How many 32K X 8 RAM chips are needed to provide a memory capacity of 256K bytes? 8 chips b. How many lines of the address must be used to access 256K bytes? How many of these lines are connected to the address inputs of all chips? using 18 address lines to address 256K memory unit using 15 address lines to address 32K memory unit c. How many lines must be decoded for the chips select inputs? Specify the size of the decoder? 3 address lines as inputs to a 3 X 8 decoder Fuw-Yi Yang 11 Text Book: Digital Design 4th Ed. Chapter 7 Problems Fuw-Yi Yang 12 Text Book: Digital Design 4th Ed. Chapter 7 Problems Fuw-Yi Yang 13