IMEC - IPQ

Report
CONFIDENTIAL
SOFI : WP3 - Silicon Chips
SOFI meeting – 20 January 2012 - Rome
SOFI REVIEW MEETING - CONFIDENTIAL
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Workpackage 3
Task 3.1: Photonic Design
Task 3.2: Waveguide process optimization
Task 3.3: Doping process
Task 3.4: Contacting process
Task 3.5: Electrical design
Task 3.6: Waveguide exposure
Task 3.7: Device fabrication
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UKA - IMEC
OPTICAL DESIGN
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Mask designs
SOFI1 (SiPP03 maskset)
- advanced passives + implants
- metallization in Ghent
- silicon fabrication finished - metallization
SOFI2 (SiPP09 maskset)
- advanced passives + implants
- CMOS compatible metallization (Leuven)
- in fabrication
SOFI2.5 (SiPP15 mask set)
- test structures for V-grooves
- tests for MMI and basic building blocks
- tests for Optical fourier transform (filters, AWGs…)
- slot waveguides
- MZI “modulators” for chalcogenide
- Resonant structures for 2.4
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SiPP09
SOFI
Loss structures
carrier modulators
electrical test structures
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SiPP09 – after maskprep
markers
and
metrology
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Dummies and tiling
Dummies on the passives
control etch rate (etch rate loading)
CMP stop in advanced passives
Tiling on metal 1
Control etch rate
Control CMP
tiles outside M1 regions
perforation inside large M1 regions
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IMEC - UKA
SLOT WAVEGUIDES
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Low loss slot waveguides
Requirement: smooth-sidewall, 100nm wide slots : 5dB/cm
Difficult:
• On the limits for 193nm dry lithography
• Needs to print on 150nm topography (close by)
• Needs sufficiently thick resist to etch 220nm
100nm
150nm
buried oxide
silicon
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3.2 Slot waveguide process
High quality slot waveguides
•Approach 0: Direct patterning
•Approach 1: two-step transfer: Failed
•Approach 2: Lithographic optimization
• Dual exposure litho (SLOT + WG) + too complex
• Phase shift mask (PSM): used for SOFI 1
• Dual exposure with PSM
•Approach 3: Separate litho layer + separate etch
•Backup: Optimize transfer process
• Approach 4: Hard mask instead of resist mask (STI): works
• Approach 5: Spacer-based (used for transistor gates)
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SOFI1 process flow for slot/socket pattering
150 nm
220 nm
SiN
Si
SiO2
Starting substrate
193 nm photo
SiN hard mask depo
HM open
BARC + Photoresist coat
220nm poly etch
PR stripped during etch
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SiN
removal
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Results (SEM images Dietmar)
incomplete etch
PSM: sidelobe patterns
design error
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Process for SOFI2: WGSLOT first
(see separate slide set)
Oxide/nitride hard mask deposition
Lithography
Etch
BARC etch
Hard-mask etch
In-situ resist strip
Silicon etch
Hard mask strip (hot phosphoric acid)
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SOFI2 etch
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Slot and WG width
520
130
500
Wire width (nm)
slot width (nm)
120
D14:dE
D23:@E
110
100
90
80
D14:dE
D23:@E
480
460
440
70
60
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Column
420
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Column
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18
IMEC
IMPLANTS
CARRIER MODULATORS
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3.3 Dopant Implantations
Implantation
•Variables: Dose, Energy, Angle
•Default Mask: 248nm litho mask (overlay alignment 150nm)
Silicidation
•Create a Si/Ni allow for an ohmic contact with metal electrodes
silicide
doped
doped
silicide
buried oxide
silicon
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Implanted device tests
Carrier dispersion modulators (running development in imec)
• Similar geometry as SiPP03 devices
• Various pn and pin waveguide geometries
• Doping test structures
Status
•Very nice results
•state-of-the art modulation efficiency and device performance
• 0.7 V.cm (interdigitated p-n junction)
• 12 Gbps MZI operation with lumped electrodes
• 40Gbps operation with TW electrodes (measurements in KIT)
• 0.5 Vpp operation (9dB ER, 10G) in ring modulator
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Eye diagrams with the lumped electrode at different bit rates
11.02 dB @4 Gbit/s
9.26 dB @10 Gbit/s
9.73 dB @8 Gbit/s
4.9 dB @12 Gbit/s
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Travelling wave electrode for 40 Gbit/s modulation
Coplanar waveguide is carefully designed
to achieve:
• 50 Ω impedance;
• low RF propagation loss;
• Velocity match with optical signal.
2
25 Gbit/s
28 Gbit/s
-log(BER)
35 Gbit/s
5
8
11
-35
35 Gbit/s
-30
-25
-20
Received Power (dBm)
-15
40 Gbit/s
For the travelling wave electrode, RF signal is boosted to 8 Vpp by an amplifier.
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IMEC
METALLIZATION
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Generation 1 (SiPP03)
Optional: Au or Al
silicide
electro-optic
cladding
Optional: Au or Al
silicide
~1um
p-doped
buried oxide
Undoped
Wire or
Slot waveguide
Optional: Au or Al
silicide
p-doped
Optional: Au or Al
p-doped
silicide
buried oxide
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Post processing 1 (Ghent)
remove silicide blok layer
Mask layer: PROCESS_CONT_4
resist
resist
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Oxide strip
Before HF
After HF
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After HF
unprotected silicide
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Post processing 2 (Ghent)
metallization
Mask layer: PROCESS_CONT_3
resist
resist
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Generation 2 (SiPP09)
Al
Al
Cu
Cu
BEOL oxide
silicide
W
electro-optic
cladding
W
silicide
p-doped
undoped
p-doped
buried oxide
Al
Al
Cu
BEOL oxide
Cu
W
silicide
electro-optic
cladding
p-doped
W
silicide
buried oxide
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Contact holes for SOFI2
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Problem: high waveguide losses
Loss, measured on full device wafers
•
•
•
•
Passive ~3-5dB/cm
Silicided: similar
After M1 (+ SiC passivation and sintering): 20dB/cm
After full passivation: 50dB/cm
all device lots which have been metallized
Cause: unknown (under investigation)
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UKA – SELEX - IMEC
RF DESIGN
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RF design of SOFI 2
Input needed from KIT and SELEX for D3.3.
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IMEC
CLADDING OPENING
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Back-end opening
Required for polymer integration
Selective stop layer on waveguide: SiC, AlOx, ...
Questions:
• Is it needed? (or is timed etch OK?)
• optical quality (index, losses, passivation)
• wet etch or dry etch?
Selective etch test planned
on back-end of carrier
dispersion modulators
Development lot in preparation
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IMEC
DEVICE FABRICATION
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Status
First generation devices : SiPP03 mask.
• Device lot out of the pilot line
• Unmetallized Samples shipped
• Metallization ongoing
Second generation devices: SiPP09 mask.
• Wafers in fabrication (FC etch)
• Expected devices: Q1/Q2 2012
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Cladding opening
Summary
Development setting up
RF electrode design
Etch experiments without
stop layer
Electrodes designed for
generation 1 and 2
Metal Contacting
Waiting for feedback of
fabrication
Tungsten contacts
Copper Heaters
Al
Aluminium Passivation
Cu
Device lot out
High losses!
Optical design
SOFI 2 mask
- SOFI modulators
SOFI 2.5 mask
- passives
Next: SOFI 3
W
silicide
Dopant Implantation
Slot patterning
100nm slot
Hard-mask based process
Seems to work. waiting for
loss measurement
SOFI REVIEW MEETING - CONFIDENTIAL
High and low doses
Control of profile
Test: pn modulators
Very good modulator
N++ N
performance
P P++
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