Chapter 4

Report
Chapter 4
Henry Hexmoor-- SIUC
• Rudimentary Logic functions:
• Value fixing
• Transferring
• Inverting
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Functions and Functional Blocks
• The functions considered are those found to be
very useful in design
• Corresponding to each of the functions is a
combinational circuit implementation called a
functional block.
• In the past, many functional blocks were
implemented as SSI, MSI, and LSI circuits.
• Today, they are often simply parts within a VLSI
circuits.
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Rudimentary Logic Functions
• Functions of a single variable X
• Can be used on the
inputs to functional
blocks to implement
other than the block’s
intended function
TABLE 4-1
Functions ofOne Variable
X
F=0 F=XF= X F=1
0
1
0
0
0
1
1
0
Value fixing
transfer
V CC or V DD
1
inverting
F= 1
F= 1
X
F= X
(c)
0
F= 0
F= 0
X
(a)
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(b)
F= X
(d)
3
1
1
Multiple-bit Rudimentary Functions
• Multi-bit Examples:
A
1
0
A
F3 A
F2 1
F1 0
F0 A
(a)
•
•
•
•
•
•
2
2
1
3
4
F
4
2:1
F
F(2:1)
(c)
0
3
(b)
F(3), F(1:0)
A wide line is used to represent
4 3,1:0
F
a bus which is a vector signal
(d)
In (b) of the example, F = (F3, F2, F1, F0) is a bus.
The bus can be split into individual bits as shown in (b)
Sets of bits can be split from the bus as shown in (c)
for bits 2 and 1 of F.
The sets of bits need not be continuous as shown in (d) for bits 3, 1, and 0
of F.
See Example 4-1
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Enabling Function
• Enabling permits an input signal to pass through
to an output
• Disabling blocks an input signal from passing
through to an output, replacing it with a fixed
value
• See Example 4-2 Automobile…
X
EN
F
(a)
X
F
EN
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(b)
Decoding
4-3
• Decoding - the conversion of an n-bit input code
to an m-bit output code with
n m  2n such that each valid code word
produces a unique output code
• Circuits that perform decoding are called
decoders
• Here, functional blocks for decoding are
– called n-to-m line decoders, where m  2n, and
– generate 2n (or fewer) minterms for the n input
variables
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Binary n-to-2n Decoders
• A binary decoder has n inputs and 2n outputs.
• Only the output corresponding to the input value is equal
to 1.
n
inputs
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:
n to 2n
decoder
:
7
2n
outputs
Decoder Examples
• 1-to-2-Line Decoder
A
D0 D1
D0 = A
0
1
1
0
0
1
D1 = A
A
(a)
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(b)
8
Decoder Examples
A0
A1 A0
D0 D1 D2 D3
A1
0
0
1
1
0
1
0
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
D0 = A 1 A 0
D1 = A 1 A 0
(a)
D2 = A 1 A 0
 Note that the 2-4-line
made up of 2 1-to-2line decoders and 4 AND gates.
D3 = A 1 A 0
(b)
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Decoder Expansion - Example
• 3-to-8-line decoder
– Number of output ANDs = 8
– Number of inputs to decoders driving output ANDs = 3
– Closest possible split to equal
• 2-to-4-line decoder
• 1-to-2-line decoder
– 2-to-4-line decoder
• Number of output ANDs = 4
• Number of inputs to decoders driving output ANDs = 2
• Closest possible split to equal
– Two 1-to-2-line decoder
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Decoder Expansion – 3-to-8 line
Example
• Result
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CS 315:
Decoding
4-3
n-to-m line: An n bit binary code is converted to a unique m bit binary pattern
See Figure 4-6 for 1-to-2 line decoder
1. Let k = n.
2. If k is even, divide k by 2 to obtain k/2. Use 2k AND gates driven by two decoders
of output size 2k/2.
3. If k is odd, obtain (k+1)/2 and (k-1)/2, Use 2K AND gates driven by a decoder of
output size 2(k-1)/2.
4. For each decoder resulting from step 2, repeat step 2 with k equal to the values
obtained in step 2 until K = 1. For k = 1, use a 1-to-2 decoder.
OR Gate
A
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Decoder Expansion
• General procedure given in book for any decoder with n
inputs and 2n outputs.
• This procedure builds a decoder backward from the
outputs.
• The output AND gates are driven by two decoders with
their numbers of inputs either equal or differing by 1.
• These decoders are then designed using the same
procedure until 1-to-2-line decoders are reached.
• The procedure can be modified to apply to decoders with
the number of outputs ≠ 2n
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Decoder Example: Seven-Segment Decoders
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/Bl
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-- don’t care inputs --
• A seven segment decoder
has 4-bit BCD input and
the seven segment display
code as its output:
• In minimizing the circuits
for the segment outputs all
non-decimal input combinations
(1010, 1011, 1100,1101, 1110,
1111) are taken as don’t-cares
14
DC
x x
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
B
x
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
a
0
1
0
1
1
0
1
0
1
1
1
0
0
0
1
0
0
b
0
1
1
1
1
1
0
0
1
1
1
0
0
1
0
0
0
c
0
1
1
0
1
1
1
1
1
1
1
0
1
0
0
0
0
d e
0 0
1 1
0 0
1 1
1 0
0 0
1 0
1 1
0 0
1 1
0 0
1 1
1 0
0 0
1 0
1 1
0 0
f
0
1
0
0
0
1
1
1
0
1
1
0
0
1
1
1
0
g
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
0
Decoder Expansion - Example
• 7-to-128-line decoder
– Number of output ANDs = 128
– Number of inputs to decoders driving output ANDs
=7
– Closest possible split to equal
• 4-to-16-line decoder
• 3-to-8-line decoder
– 4-to-16-line decoder
• Number of output ANDs = 16
• Number of inputs to decoders driving output ANDs = 2
• Closest possible split to equal
– 2 2-to-4-line decoders
– Complete using known 3-8 and 2-to-4 line
decoders
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Decoder with Enable
• In general, attach m-enabling circuits to the outputs
• See truth table below for function
– Note use of X’s to denote both 0 and 1
– Combination containing two X’s represent four binary combinations
• Alternatively, can be viewed as distributing value of signal
EN
EN to 1 of 4 outputs
A
• In this case, called a
A
demultiplexer
D
1
0
0
EN A 1 A 0
0
1
1
1
1
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X
0
0
1
1
X
0
1
0
1
D0 D1 D2 D3
0
1
0
0
0
(a)
0
0
1
0
0
0
0
0
1
0
D1
0
0
0
0
1
D2
D3
16
(b)
Encoding
4-4
• Encoding - the opposite of decoding - the
conversion of an m-bit input code to a n-bit output
code with n m  2n such that each valid code
word produces a unique output code
• Circuits that perform encoding are called encoders
• An encoder has 2n (or fewer) input lines and n
output lines which generate the binary code
corresponding to the input values
• Typically, an encoder converts a code containing
exactly one bit that is 1 to a binary code corresponding to the position in which the 1 appears.
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Encoder
n
2n
inputs
I0
I1
I2
…
I2n-1
I1,I3, I5, I7
>
m
Encoder
OR0
Y0
Y1
n outputs
…
Y n-1
0th bit
Y0 = 0001 + 0011 + 0101 + 0111
I2, I3, I6, I7
OR1
y1
I4, I5, I6, I7
OR2
y2
2n – n encoder requires “n 2n-1 input” OR gates
Bit j of input code is connected to OR gate j if bit j in the input is 1.
Encoders are useful when the occurrence of one of several disjoint events needs to be
represented by an integer identifying the event. E.g., wind direction encoder
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Encoder Example 1
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Encoder Example 2
• A decimal-to-BCD encoder
– Inputs: 10 bits corresponding to decimal
digits 0 through 9, (D0, …, D9)
– Outputs: 4 bits with BCD codes
– Function: If input bit Di is a 1, then the
output (A3, A2, A1, A0) is the BCD code for i,
• The truth table could be formed, but
alternatively, the equations for each of the four
outputs can be obtained directly.
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Encoder Example (continued)
• Input Di is a term in equation Aj if bit Aj is 1 in the
binary value for i.
• Equations:
A3 = D8 (1000) + D9 (1001)
A2 = D4 (0100)+ D5 (0101) + D6 (0110)+ D7 (0111)
A1 = D2 (0010)+ D3 (0011) + D6 (0110) + D7 (0111)
A0 = D1 (0001)+ D3 (0011)+ D5 (0101) + D7 (0111) + D9
(1001)
• F1 = D6 + D7 can be extracted from A2 and A1.
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Priority Encoder
• If more than one input value is 1, then the encoder
just designed does not work.
• One encoder that can accept all possible
combinations of input values and produce a
meaningful result is a priority encoder.
• Among the 1s that appear, it selects the most
significant input position (or the least significant input
position) containing a 1 and responds with the
corresponding binary code for that position.
• Priority encoders are useful when inputs have a
predefined priority, e.g., interrupt requests from
peripheral devices
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A1 = D3’D2 + D3
Priority Encoder Example
A0 = D3’D2’D1 + D3
V = D0 + D1+ D2+ D3
• Priority encoder with 5 inputs (D4, D3, D2, D1, D0) - highest
priority to most significant 1 present - Code outputs A2, A1, A0
and V where V indicates at least one 1 present.
No. of Minterms/Row
D4
1
0
0
1
0
2
Outputs
Inputs
D3 D2
D1
D0
A2
A1
A0
V
0
0
0
X
X
X
0
0
0
0
1
0
0
0
1
0
0
0
1
X
0
0
1
1
4
0
0
1
X
X
0
1
0
1
8
0
1
X
X
X
0
1
1
1
16
1
X
X
X
X
1
0
0
1
• Xs in input part of table represent 0 or 1; thus table entries
correspond to product terms instead of minterms. The column
on the left shows that all 32 minterms are present in the product
terms in the table
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Selecting
4-5
• Selecting of data or information is a critical function in
digital systems and computers
• Circuits that perform selecting have:
– A set of information inputs from which the selection is made
– A single output
– A set of control lines for making the selection
• Logic circuits that perform selecting are called
multiplexers
• Selecting can also be done by three-state logic or
transmission gates
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Multiplexers
• A multiplexer selects information from an
input line and directs the information to an
output line
• A typical multiplexer has n control inputs (Sn n information
,
…
S
)
called
selection
inputs,
2
1
0
inputs (I2n - 1, … I0), and one output Y
• A multiplexer can be designed to have m
information inputs with m <2n as well as n
selection inputs
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Selecting
4-5
Multiplexers, data selectors
2n input lines + n selection inputs
See 2-to-1-line multiplexer in Figure 4-13
Two input lines and one select line S
Y = S’I0 + S I1
Enabling
Circuits
Decoder
OR Gate
A
I0
Y
S
I1
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2-to-1-Line Multiplexer
• The single selection variable S has two values:
– S = 0 selects input I0
– S = 1 selects input I1
• The equation:
• The circuit:
Y=
S’I0 + SI1
Enabling
Circuits
Decoder
I0
Y
S
I1
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2-to-1-Line Multiplexer (continued)
• Note the regions of the multiplexer circuit shown:
– 1-to-2-line Decoder
– 2 Enabling circuits
– 2-input OR gate
• To obtain a basis for multiplexer expansion, we combine
the Enabling circuits and OR gate into a 2  2 AND-OR
circuit:
– 1-to-2-line decoder
– 2  2 AND-OR
• In general, for an 2n-to-1-line multiplexer:
– n-to-2n-line decoder
– 2n  2 AND-OR
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Example: 4-to-1-line Multiplexer:
n = 2 selection bits
• 2-to-22-line decoder
• 22  2 AND-OR
Decoder
S1
4
S0
S1
S0
2 AND-OR
Decoder
I0
Y
I1
Y
I2
I3
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Multiplexer Width Expansion
• Select “vectors of bits” instead of “bits”
• Use multiple copies of 2n  2 AND-OR in parallel
• Example:
4-to-1-line
quad multiplexer
• Figure 4-16
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Using Multiplexers
• Any Boolean function can be implemented by
setting the inputs corresponding to the function
as inputs and the selectors as the variables.
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Shifters
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Rotator
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Parity for six bit messages
Even Parity Generator Circuit
B0
B1
B2
B3
B4
B5
B6
B even
Even Parity Checker Circuit
B0
B1
B2
B3
B4
B5
B6
ERROR
B even
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Example: Gray to Binary Code
• Design a circuit to
convert a 3-bit Gray
code to a binary code
• The formulation gives
the truth table on the
right
• It is obvious from this
table that X = C and the
Y and Z are more complex
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Gray
ABC
000
100
110
010
011
111
101
001
Binary
xyz
000
001
010
011
100
101
110
111
Gray to Binary (continued)
• Rearrange the table so that the input combinations are in
counting order, pair rows, and find rudimentary functions
Gray
ABC
Binary
xyz
000
000
001
111
010
011
011
100
100
001
101
110
110
010
111
101
Henry Hexmoor
Rudimentary
Functions of
C for y
Rudimentary
Functions of
C for z
F=C
F=C
F=C
F=C
F=C
F=C
F=C
F=C
36
Gray to Binary (continued)
• Assign the variables and functions to the multiplexer inputs:
C
C
C
C
C
C
A
B
Henry Hexmoor
D00
D01
D02
D03
S1
S0
C
C
C
D10
D11
D12
D13
A
B
S1
S0
C
Out
8-to-1
MUX
Y
37
Out
8-to-1
MUX
Z
Combinational Function Implementation
4-6
• Alternative implementation techniques:
– Decoders and OR gates
– Multiplexers (and inverter)
– ROMs
– PLAs
– PALs
– Lookup Tables
• Can be referred to as structured implementation methods since a
specific underlying structure is assumed in each case
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Read Only Memory
• Functions are implemented by storing the truth table
• Other representations such as equations more
convenient
• Generation of programming information from
equations usually done by software
• Text Example 4-10 Issue
– Two outputs are generated outside of the ROM
– In the implementation of the system, these two functions are
“hardwired” and even if the ROM is reprogrammable or
removable, cannot be corrected or updated
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Programmable Logic Array Example
A
B
C
X
X
X
1
X
X
X
2
X
X
X Fuse intact
1 Fuse blown
X
X
X
3
X
X
X
4
X
X
X
C C B B A A
0
X
1
F1
F2
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Lookup Tables
• Lookup tables are used for implementing
logic in Field-Programmable Gate Arrays
(FPGAs) and Complex Logic Devices
(CPLDs)
• Lookup tables are typically small, often with
four inputs, one output, and 16 entries
• Since lookup tables store truth tables, it is
possible to implement any 4-input function
• Thus, the design problem is how to optimally
decompose a set of given functions into a set
of 4-input two- level functions.
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HW 4
1. Draw the detailed logic diagram of a 3-to-8line decoder using only NOR and NOT
gates. Include an enable input. Q4-9
2. Implement a binary full adder with a dual 4to-1-line multiplexer and a single inverter.
Q4-23
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