Presentation kit - UCSD VLSI CAD Laboratory

Report
Toward Quantifying the IC Design Value of
Interconnect Technology Improvement
Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li
VLSI CAD LABORATORY, UC San Diego
http://vlsicad.ucsd.edu
UC San Diego / VLSI CAD Laboratory
Outline
Motivation
 Related Work

Our Framework
 Experiments and Results


Conclusion
-2-
Outline
Motivation
 Related Work

Our Framework
 Experiments and Results


Conclusion
-3-
Motivation





Wire delay increases with technology scaling
Improvement of BEOL both important and expensive
Issue 1: no systematic quantification of ROI from BEOL
improvement
Issue 2: unclear whether BEOL improvement benefits can
be leveraged by EDA tools
Goals:
– A framework to quantify BEOL improvement values
 guide BEOL technology investment and targets
– Assess EDA tools’ ability to leverage improved BEOL
= potential “EDA gap”
-4-
Focus of Our Work


Product quality comes from interaction among design,
BEOL technology, EDA tool
We focus on interaction between BEOL and EDA
This work
EDA tool
BEOL
Technology
Design
-5-
Outline
Motivation
 Related Work

Our Framework
 Experiments and Results


Conclusion
-6-
Related Work







Studies of DRAM or simple logic circuits, not at chip-level
Ignores interaction between BEOL technology, EDA tool
[Li01] – DRAM performance improvements from low-k
[Kapur02] – R, C impacts on signal, power
[Bamal06] – Performance, energy comparison studies
with different interconnect technologies
Focus on variation, not future BEOL improvements
[Jeong10] – Chip-level impacts of interconnect variation
due to double-patterning
-7-
Outline
Motivation
 Related Work

Our Framework
 Experiments and Results


Conclusion
-8-
Our Framework
Original
BEOL files
Hypothetical
RC reductions
Modified
BEOL files
Designs
Circuit implementation flow
(synthesis, place and route)
Circuit
implemented
with original
BEOL
Circuit
implemented
with modified
BEOL
Timing and power analysis
1. Modify BEOL files to model
R, C reductions in future
technologies
– Modify ITF files
– Use Synopsys StarRC to
convert ITF to TLUplus files
2. Design implementation
(RTL-to-layout and signoff)
with original and modified
BEOL files
3. Run timing, power analysis
-9-
Testbed


Designs: {aes_cipher, des_perf, mpeg2, pci_bridge32}
from OpenCores x {fast, slow} clock periods
Technology: TSMC 45nm, LVT and HVT
20SOC and below can be very different

SP&R: Synopsys Design Compiler + IC Compiler
– Execute each P&R run three times  denoising


Timing and power analysis: Synopsys IC Compiler
Signoff: no hold or EM violation, TNS < 30ps
 Apples-to-apples comparison for design metrics
-10-
Outline
Motivation
 Related Work

Our Framework
 Experiments and Results


Conclusion
-11-
Expt 1: Impact of R, C Reduction on Power



45% R, C reduction only leads to 8% power reduction
R, C reduction improves timing  fewer / smaller cells
 leakage power ↓ (but, only on critical paths)
C reduction  load cap ↓  net switching power ↓
(but, gate cap dominates)
Normalized Power
1.1
min
average
max
linear
Power of implementation
with original BEOL
1.0
0.9
0.8
0.7
R, C=α%: implementation with
α% dielectric constant and metal
resistivity w.r.t original BEOL
0.6
R, C reduction occurs on M2-M5
R, C=55%
R, C=70%
R, C=85%
R, C=100%
-12-
Impact of R, C Reduction on Area


R, C reduction leads to little improvement in area
Tool uses Vt swapping to exploit improved timing
– Same footprint of LVT and HVT cells  same post-opt area
Optimization methodology of EDA tools affects value
extracted from improved BEOL
1.1
Normalized Area

min
average
max
linear
Area of implementation
with original BEOL
1.0
0.9
0.8
0.7
0.6
R, C=55%
R, C=70%
R, C=85% R, C=100%
-13-
Expt 2: Reduction in R vs. in C


In this experiment, C reduction offers more benefits
– Wire delay ↓  trade timing for power
– R reduction improves wire delay
– C reduction improves wire delay + load cap
R reduction can be critical with high Vdd, temperature
Technology R&D might focus more on C reduction
Power w/ only R reduction
min
average
max
linear
1.0
0.9
0.8
0.7
1.1
Normalized Power
Normalized Power
1.1
Power w/ only C reduction
min
average
max
linear
1.0
0.9
0.8
0.7
R=55%
R=70%
R=85%
R=100%
C=55%
C=70%
C=85%
C=100%
-14-
Expt 3: R, C Reduction in Advanced Technology

Wire delay becomes critical in advanced technologies
– Impact of R reduction increases
– We model advanced technology = increase R by 8x

Benefits of R, C reduction increase in advanced technologies
Leakage power
Advanced
Current
5%
1.0
2%
0.9
0.8
0.7
R=55%
C=55%
R, C=55%
Normalized Total Power
Normalized Leakage
1.1
Total power
1.1
Advanced
Current
1.0
0.9
0.8
0.7
R=55%
C=55%
R, C=55%
-15-
Expt 4: Impact of Layer Selection

BEOL improvement incurs high manufacturing cost
– What is optimum subset of layers to improve under cost limits?
– Flexible BEOL = subset of layers is selectively improved
– Inappropriate selection of R, C-reduced layers is suboptimal
Guideline: reduce R, C on adjacent and highly utilized layers
Small difference between different layer selections
– Tools’ ability to leverage the improved BEOL layers?
1.1
Normalized Power

min
average
RC-reduced layers are
far from each other
max
1.0
RC reduction has more
benefit on highly utilized
layers
0.9
0.8
{2,3,4,5}
{2,3}
{2,4}
{2,5}
{3,4}
{3,5}
Layers with improved BEOL
{4,5}
-16-
Tools’ Exploitation of R, C Reduction

Assessment flow
1. Implement designs with both original and improved BEOL
2. Run timing and power analysis with improved BEOL
3. Compare frequency, power

Preliminary results show tool can leverage R, C reduction
– Case 1 might be misguided during optimization
12
13
Reduced R, C on M2, M5
12
11
Power (mW)
Power (mW)
Reduced R, C on M3, M4
10
9
11
10
9
8
8
800
850
900
950
Frequency (MHz)
1000
1050
800
850
900
950
Frequency (MHz)
1000
Case 1: Implementation with original BEOL, analyzed with modified BEOL
Case 2: Implementation with modified BEOL, analyzed with modified BEOL
1050
-17-
RC-Awareness in EDA Tools

A “smart” router should be aware of improved BEOL
– Route setup critical paths on layers with small R, C
– Route hold critical paths on layers with large R, C

∆wire distribution (of layer x)
= %wire on layer x - %wire on layer x
w/ improved BEOL

w/ original BEOL
Assessment:
– Implement designs with flexible BEOL
– Check ∆wire distribution of layers for setup- and
hold-critical nets
-18-
Experimental Results
Compare ∆wire distribution from current router (bars)
and a hypothetical RC-aware router (ovals)

– White (Orange) = positive (negative) ∆wire distribution
– Same color of bar and dotted oval  RC-awareness
Router is not fully responsive to BEOL R, C reduction

∆Wire distribution
Setup-critical nets
8%
0%
-8%
8%
0%
-8%
8%
0%
-8%
8%
0%
-8%
Hold-critical nets
√ √ √ √
√ √
√
X
X
√
X
√
√
{2,3,4,5} {2,3} {2,4} {2,5}
√
√ X
{3,4} {3,5}
Layers with reduced RC
{4,5}
8%
0%
-8%
8%
0%
-8%
8%
0%
-8%
8%
0%
-8%
√ X X X
√ X
X
X
M2
X X
√
X
X
{2,3,4,5} {2,3} {2,4} {2,5} {3,4}
M3
X
M4
√ X
M5
{3,5}
Layers with reduced RC
{4,5}
-19-
Outline
Motivation
 Related Work

Our Framework
 Experiments and Results


Conclusion
-20-
Conclusion


Framework to quantify impact of interconnect
resistance and/or capacitance reductions on chip-level
design metrics
Reduction in capacitance gives more benefits than in
resistance
– R reduction can be critical in wire-delay dominant designs
(due to high Vdd, temperature or advanced technology)


Capability of EDA tools to leverage improved BEOL has
room for improvement
Ongoing works
– Iso-constraints vs. iso-GDS
-21-
ISO-GDS Expt

Basic tradeoffs to exploit improved BEOL
– R, C reduction  improved timing  Vdd ↓  Power ↓
Vdd reduction
100%
98%
Performance
requirement
+ device type
Activity factor
+ nominal voltage
+ device type
96%
94%
92%
0%
10%
Frequency improvement
10%
20%
30%
40%
Power reduction
R, C reduction
100%
8%
96%
6%
92%
4%
Gate-wire
balance
2%
0%
0%
10%
20%
30%
R, C reduction
40%
88%
84%
0%
10%
20%
30%
R, C reduction
40%
-22-
Conclusion


Framework to quantify impact of interconnect
resistance and/or capacitance reductions on chip-level
design metrics
Reduction in capacitance gives more benefits than in
resistance
– R reduction can be critical in wire-delay dominant designs
(due to high Vdd, temperature or advanced technology)


Capability of EDA tools to leverage improved BEOL has
room for improvement
Ongoing works
– Iso-constraints vs. iso-GDS
– Study impact of interconnect R, C reduction across wide
supply voltages
– Extend our analyses to M1 and middle-of-line layers
-23-
Acknowledgments

Work supported from Sandia National Labs,
Qualcomm, Samsung, NSF, SRC, the
IMPACT (UC Discovery) and IMPACT+
centers
-24-
Thank You!
Backup Slides
Values of Improved BEOL

Question 1: What is overall impact of R and/or C
reduction(s) on design metrics?
– 45% R, C reduction  8% power reduction, similar area

Question 2: Which reductions offer more benefits, in R
or in C?
– C reduction offers more benefits
– R reduction can be critical with high Vdd, temperature

Question 3: How will impacts of R, C reduction change
in advanced technology nodes?
– Benefits of R, C reduction increase in advanced technology

Question 4: What is optimum subset of layers to improve
under cost limits?
– Should reduce R, C on adjacent and highly utilized layers
-27-

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