April 30, 2014

Report
Cost efficient soft-error
protection for ASICs
Tuvia Liran; Ramon Chips Ltd.
[email protected]
April 30, 2014
1
What is soft error
An error in the functionality of the chip/system
due to corruption of data
Hard error: An error in the functionality of the
chip/system due to permanent damage
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Key topics
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SE basics
Sources and mechanisms of SE
Single event effects
Methodologies for SE mitigation
Summary
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Terminology
• SE
• SER
• SEE
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– SEU
– SET
– SEL
SEFI
LET
SBU
MCU
MBU
MTTF
FIT
- Soft Error
- Soft Error Rate
– Single Event Effect
– Single Event Upset
– Single Event Transient
– Single Event Latch-up
– Single Event Functional Interrupt
– Rate of energy loss in Si/SiO2 [Mev/mg/cm2]
- Single bit upset
- Multi-cell upset
– Multi Bit Upset
– Mean Time to Fail
– Failure in Time; =10-9/MTTF(h)
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Myth Blasting
• SE is relevant only for space environment
• SE is affecting memory cells only
• SE is not a reliability issue
• DRAM is more sensitive to SE than SRAM
• Latchup cannot cause SE
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Sources of soft-errors
• Terrestrial:
– Interactions with cosmic
particles (Neutrons)
– Alpha particles from
die/package
• Space:
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Protons (>93%)
Alpha (~6%)
Neutrons
Electrons
Alpha and heavy particles
(up to 500Mev)
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Interaction of Neutrons
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Typical flux – 20N/h/cm2 @sea level (NYC)
Energy of cosmic Neutron – 20-300Mev
Strong dependence on altitude
Higher concentration in polar areas (Lat >60)
Interaction with Boron (20% of B10) , mostly in BPSG
(@≥0.25µ) – most dominant effect
• Interacts with various nuclei (W, Si, Pb,Au …)
• Shielding is not practical
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Alpha particles
• Alpha particle == He++
• Energy: 1-6MeV / particle (1.5Mev from N->B10)
– ~3.6eV requires to generate e-h pair
• Penetration range in Si – 15-30µ
• Generating ~45fQb / Mev
– Critical charge of SRAM cell is ~1fQb
– No SEU immune SRAM cell is not practical in VDSM
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SEU in SRAM
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SBU/MCU in SRAM
Single bit upset
Multi cell upset
Multi cell upset ≠ Multi bit upset
High MUX ratio -> lower MBU
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Single Event Transient (SET)
• Pulses at logic nodes, caused by ionizing particles
• Typical pulse width is 10÷200pS (@Alpha)
• Such pulses might cause:
– Permanent error if sampled by FF
– Permanent error if activates asynchronous signals
P(error)=T(pulse)/T(period)
=T(pulse)*F
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BER [log]
Frequency dependence of SEU/SET
lS
Tota
EE
SEU
SET
Frequency [log]
Lower effective frequency, such as by clock gating, reduces SET
SET can be mitigated by glitch filtering before sampling
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Effective glitch filtration
Glitch filtering
• Narrow pulses are filtered
by C-element+delay
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Weak SCAN mux
• Implementing resistive MUX
at the input of the flip-flop
will filter narrow glitches
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Impact of scaling
• Scaling reduces the “critical charge”
• Faster devices do not “filter” narrow SET pulses
• More devices/memory per chip – more sensitive
elements
• Higher frequency increases the probability to SET
• SE is a major issue in advanced UDSM
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SEE mitigation concepts
• S/W techniques for error correction
– Example: 3 processing + voting
• Mitigation at system level
– Example: TMR
• Mitigation at chip level
– Example: EDAC, SE protected FFs
• Mitigation by circuit
– Example: SE protected FFs & SRAM cells
• Mitigation by Si process
– Example: SOI (poor !!!)
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SEE sensitivity - application
• Types of data, sorted by SEE sensitivity:
– Configuration (FPGA, CNFREG…)
– Control logic (FSM, uCode,…)
– Executable data (.exe files, I-Cach,…)
– Stored data (databases, D-Cach, …)
– Temporary data (Video, Audio, …)
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Summary
• SEE is becoming a significant reliability issue in VDSM
technologies
• SRAMs are typically the most sensitive elements to
SEE
• SE mitigation is possible, mostly by digital techniques
and proper methodologies and tools
• Availability of EDA tools for analyzing SER and
mitigating SEE is limited. Optima presents a very
interesting tool.
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