Onchip Interconnect Exploration for Multicore Processors Utilizing FPGAs Graham Schelle and Dirk Grunwald University of Colorado at Boulder.

Report
Onchip Interconnect
Exploration for Multicore
Processors Utilizing
FPGAs
Graham Schelle and Dirk Grunwald
University of Colorado at Boulder
Outline
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Network on Chip (NoC) defined
Current onchip interconnect tools
NoCem (NoC Emulator) specification
What else is needed before release
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We want it to be used…and cited
Conclusions
Network on Chip Defined (in 1 slide!)
Power/design
concerns in modern
processors lead to
multicore chips
Transistors seen as
“free” allowing more
transistors for noncomputational tasks
Network on
Chip
High speed clocking
leads to signals not
propagating across
chip in single cycle
Networking scales to
infinite number of
access points and is
well understood
Onchip Interconnects for FPGAs
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Existing Buses on FPGAs
PLB,OPB,FSL
 Can have multiple masters (e.g. processors)
 Scale well for current uses of FPGAs
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Existing NoCs
Research projects
 Proprietary projects
 Application specific (streaming…)
 Not built for parameterization, some other VALID
focus
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NoCem Specification
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Synthesizable VHDL
Heavy use of generics / generate statements
Requires minimal Xilinx IP (FIFOs…)
To modify anything
Change generics, everything automatically generated
 E.g. to go from 2x2 mesh with 16b datawidth to 4x4
torus with 8b datawidth, change 3 lines of code!
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NoCem Interface
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FIFO-ish
Enqueue and dequeue path for every access point
 Packet Control and Data paths
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Meaning of those paths depends on NoC
configuration
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Datapath
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Only variable width. Length of packet determined by
packet control
Packet control: src, dest, packet length
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Underlying Network reads toplevel packet structure, reads
correct fields at correct times
NoCem Bridges
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Use Existing Buses, bridge to NoC
Integration into existing Xilinx tool flows
 NoC can look like memory, SoC, …
 Use IPIF interface
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PLB, OPB
Different bus widths…
 But processors both 32b
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How Big is NoCem?
NoC
Dimensions
2x2
3x3
4x4
2x2
3x3
4x4
Datawidth
LUTs
16b
16b
16b
32b
32b
32b
4,086
11,693
21,570
5,822
16,394
34,370
xc2vp30
LUTs used
14%
42%
78%
21%
59%
125%
Mesh, 16-deep channel FIFOs, RR Arbitration
Example Uses
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Memory Architecture (in paper)
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Asymmetric Processor Configuration
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Various distributed cache configurations
Using Microblaze, PowerPC
Special Processor Offloads
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Floating Point, Network Processing
All can be emulated over NoC using NoCem…
For Release
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We want NoCem to be used!
Already in use at CU Boulder
 Full source will be made available online
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To do for release
Clean/zip up code
 Some Documentation
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ETA: April 2006
Conclusions
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NoCem as a research tool
Open source
 Non-proprietary
 Non application Specific
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NoCem for multicore processor research
Allows NoC exploration
 Easy integration into Xilinx EDK flow
 Useful for a variety of research topics in this space
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Any Questions?

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