### Uppu

```CPU Design-Project
{
Multicycle Datapath with Finite
State Machine as Control Unit
N.S.V Ravi Tej Uppu
Core Instruction set:Name
Mnemic
Format
Operation
Opcode
R
R[rd] = R[rs] + R[rt]
0000
And
and
R
R[rd] = R[rs] & R[rt]
0001
Or
or
R
R[rd] = R[rs] | R[rt]
0010
Subtract
sub
R
R[rd] = R[rs] - R[rt]
0011
Not
not
R
R[rd] = nt[ R[rs] | \$0]
0100
Xor
xor
R
R[rd] = R[rs] xor R[rt]
0101
lw
I
R[rt]=M(R[rs]+signExtImm)
0110
Store word
sw
I
M(R[rs]+signExtImm)=R[rt]
0111
I
R[rt] = R[rs] + signExtImm
1000
And Imm
andi
I
R[rt] = R[rs] & signExtImm
1001
Or Imm
ori
I
R[rt] = R[rs] | signExtImm
1010
Branch on equal
beq
I
if R[rs]==R[rt],PC=PC+4+brn
1011
Halt
hlt
J
PC = PC - 1
1100
Jump
j
J
1101
Set on less than
slt
R
R[rd] = (R[rs]<R[rt]) ? 1 : 0
1110
Basic Instruction Formats:
R
15 opcode 12 11 rs 8 7
I
15 opcode 12 11
J
15 opcode 12 11
rt
rs 8 7 rt
4
3
rd
0
4 3 immediate 0
0
Register Name, Number, Use:
Name
Number
Use
\$zero
0
the constant value ‘0’
\$at
1
assembler Temporary
\$v0
2
values for function results
\$a0-\$a3
3-6
arguments
\$t0-\$t3
7-10
temporary registers
\$s0-\$s3
11-14
saved temporary
\$ra
15
Multicycle Datapath with Control unit:
Memory
Mem data
Write data
Memory
Data
Register
rt
0
data 1
Reg-file
Write reg
data 2
Write data
1
2
A
zero
AL
Uop
B
1
-1
Sign
Exten
d
1 mux 0
Inst(15-12)
Instruction(
11-8)
Instruction(
7-4)
(Inst Reg) rd
Instruction(
4-0)
r
s
3 2 1 0
PC
1 mux 0
IRWrite
ALUSrcA
RegWrite
Regdst
Inst(0-11) & PC(12-15)
1 mux 0
o/p’s
PCWrite
Contr
ol
IorD
Mem Write Op(30)
MemtoReg
PCSource
ALUop
ALUSrcB
1 mux 0
PCWriteCond
Finite State Machine Control:
Instruction Fetch
Instruction Decode
0
Start
1
ALUSrcA=0
IorD=0,IRwrt
ALUSrcB=01
ALUOp=000
PCwrite=1
PCSource=00
ALUSrcA=0
ALUSrcB=10
ALUop=000
2
Exec
ALUSrcA=1
ALUSrcB=0
0
AlUop=000
MemAccs
3
6
8
ALUSrcA=1
ALUSrcB=00
ALUop=
opcode(2-0)
ALUSrcA=1
ALUSrcB=00
ALUop=011
PCwritecond
PCSource=01
MemAccs
IorD=
1
4 RegDst=
0
Regwrite
Memto
Reg=1
R-type Comp
5
Memwrite
IorD=1
Jmp
Comp
Branch Comp
7
RegDst=1
Regwrite
Memtore
g=0
9
PCwrite
PCSource
=10
Defining The Control Signals:
Signal Name\state
0
1
2
3
4
5
6
7
8
9
RegDst
0
0
0
0
0
0
0
1
0
0
RegWrite
0
0
0
0
1
0
0
1
0
0
ALUSrcA
0
0
1
1
1
1
1
1
1
0
MemWrite
0
0
0
0
0
1
0
0
0
0
MemtoReg
0
0
0
0
1
0
0
0
0
0
IorD
0
0
0
1
0
1
0
0
0
0
IRWrite
1
0
0
0
0
0
0
0
0
0
PCWrite
1
0
0
0
0
0
0
0
0
1
PCWriteCond
0
0
0
0
0
0
0
0
1
0
ALUop
000 00
0
000
000
000
000
000
001
010
011
100
000
010
000
ALUSrcB
01
10
10
10
10
10
00
00
00
00
PCSource
00
00
00
00
00
00
00
00
01
10
Test Program:
High Level Language
Assembly Language
Machine Language
lw \$t0,0(\$t1)
beq \$t0,\$s1,Exit
j loop
0000 0000
While (save[i] < k)
i += 1;
Assuming:
i -> \$s0
k -> \$s1
101 100
1
0
0000 1110 1000 1000
0110 1000 0111 0000
1011 1100 1000 Exit
1000 1001 0001 1001
1101
Exit:
1000 0000 0000 1100
Future modifications:
- Make changes in the core instruction set and add instructions
like
(a) Jump register
(b) Shift left logic
-Implement the control unit as a Micro Computer using:
(a) Micro Instructions
(b) Microprogramming.
-Make effective use of the registers defined.
Conclusion:
The above designed CPU can execute a sequence of
instructions which include R-type, Data transfer, branching
etc., while its operations for programs which include functions
is to be tested.
Questions
Thank you!
```