Lecture 12b adders

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Lecture 12b:
Adders
Generate / Propagate
 Equations often factored into G and P
 Generate and propagate for groups spanning i:j
G i : j  G i : k  Pi : k
Pi : j  Pi :k
G k  1: j
Pk  1: j
0:0 0:0
0 in GC P 
 Base case
G i :i  G i  Ai
Bi
Pi :i  Pi  Ai  B i
G 0:0  G 0  C in
P0:0  P0  0
 Sum:
S i  Pi  G i  1:0
17: Adders
CMOS VLSI Design 4th Ed.
2
PG Logic
A4
B4
A3
B3
A2
B2
A1
B1
Cin
1: Bitwise PG logic
G4
P4
G3
P3
G2
P2
G1
P1
G0
P0
2: Group PG logic
G3:0
G2:0
G1:0
G0:0
C3
C2
C1
C0
3: Sum logic
C4
Cout
17: Adders
S4
S3
S2
S1
CMOS VLSI Design 4th Ed.
3
Carry-Ripple Revisited
G i :0  G i  Pi
G i 1:0
A4
B4
G4
P4
A3
B3
G3
P3
A2
B2
G2
P2
A1
B1
G1
P1
Cin
G0
G3:0
G2:0
G1:0
G0:0
C3
C2
C1
C0
P0
C4
Cout
17: Adders
S4
S3
S2
S1
CMOS VLSI Design 4th Ed.
4
Carry-Ripple PG Diagram
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
t ripple  t pg  ( N  1) t A O  t xor
Delay
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
17: Adders
CMOS VLSI Design 4th Ed.
5
Carry-Skip Adder
 Carry-ripple is slow through all N stages
 Carry-skip allows carry to skip over groups of n bits
– Decision based on n-bit propagate signal
Cout
A16:13 B16:13
A12:9 B12:9
A8:5 B8:5
A4:1
P16:13
P12:9
P8:5
P4:1
1
0
C12
+
S16:13
17: Adders
1
0
C8
+
S12:9
1
0
C4
+
S8:5
CMOS VLSI Design 4th Ed.
B4:1
1
Cin
0
+
S4:1
6
Carry-Skip Adder
 Carry-ripple is slow through all N stages
 Carry-skip allows carry to skip over groups of n bits
– Decision based on n-bit propagate signal
Cout
A32:25 B32:25
A24:17 B24:17
A16:9 B16:9
A8:1
P32:25
P24:17
P8:5
P8:1
1
0
C24
+
S32:25
17: Adders
1
0
C16
+
S24:17
1
0
C8
+
S16:9
CMOS VLSI Design 4th Ed.
B8:1
1
Cin
0
+
S8:1
7
Carry-Lookahead Adder
 Carry-lookahead adder computes Gi:0 for many bits
in parallel.
 Uses higher-valency cells with more than two inputs.
A16:13 B16:13
Cout
G16:13
P16:13
+
S16:13
17: Adders
C12
A12:9 B12:9
G12:9
P12:9
+
S12:9
A8:5 B8:5
C8
A4:1
C4
G8:5
P8:5
B4:1
G4:1
P4:1
+
+
S8:5
S4:1
CMOS VLSI Design 4th Ed.
Cin
8
Carry-Lookahead Adder
 Carry-lookahead adder computes Gi:0 for many bits
in parallel.
 Uses higher-valency cells with more than two inputs.
A32:25 B32:25
Cout
G32:25
P32:25
+
S32:25
17: Adders
C24
A24:17 B24:17
G24:17
P24:17
+
S24:17
C16
A16:9 B16:9
G16:9
P16:9
+
S16:9
CMOS VLSI Design 4th Ed.
A8:1
C8
B8:1
G8:1
P8:1
+
Cin
S8:1
9
Tree Adder
 If lookahead is good, lookahead across lookahead!
– Recursive lookahead gives O(log N) delay
 Many variations on tree adders
17: Adders
CMOS VLSI Design 4th Ed.
10
PG Diagram Notation
Black cell
i:k
Gray cell
k-1:j
i:k
i:j
Gi:k
Pi:k
Gk-1:j
Pk-1:j
17: Adders
Buffer
k-1:j
i:j
i:j
i:j
Gi:j
Gi:k
Pi:k
Gk-1:j
Pi:j
CMOS VLSI Design 4th Ed.
Gi:j
Gi:j
Gi:j
Pi:j
Pi:j
11
Sklansky
15 14 13 12 11 10
15:14
13:12
11:10
15:12 14:12
15:8
14:8
11:8 10:8
13:8
9
9:8
8
7
6
7:6
7:4
5
5:4
6:4
4
3
2
3:2
3:0
1
0
1:0
2:0
12:8
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
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CMOS VLSI Design 4th Ed.
12
Brent-Kung
15 14 13 12 11 10
15:14
13:12
15:12
11:10
9
9:8
11:8
8
7
7:6
6
5
5:4
7:4
15:8
4
3
3:2
2
1
0
1:0
3:0
7:0
11:0
13:0
9:0
5:0
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
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CMOS VLSI Design 4th Ed.
13
Kogge-Stone
15:14 14:13 13:12 12:11 11:10 10:9
9:8
8:7
7:6
6:5
5:4
4:3
3:2
2:1
3:0
2:0
15:12 14:11 13:10
12:9
11:8 10:7
9:6
8:5
7:4
6:3
5:2
4:1
13:6
12:5
11:4 10:3
9:2
8:1
7:0
6:0
5:0
4:0
15:8
14:7
1
2
3
4
5
6
7
8
9
15 14 13 12 11 10
0
1:0
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
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CMOS VLSI Design 4th Ed.
14
Han-Carlson
15 14 13 12 11 10
9
8
7
6
5
4
3
15:14
13:12
11:10
9:8
7:6
5:4
3:2
15:12
13:10
11:8
9:6
7:4
5:2
3:0
15:8
13:6
11:4
9:2
7:0
5:0
2
1
0
1:0
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
17: Adders
CMOS VLSI Design 4th Ed.
15
Knowles [2, 1, 1, 1]
15 14 13 12 11 10
9
8
7
6
5
4
3
2
15:14 14:13 13:12 12:11 11:10 10:9
9:8
8:7
7:6
6:5
5:4
4:3
3:2
2:1
15:12 14:11 13:10
3:0
2:0
15:8
14:7
13:6
12:9
11:8 10:7
9:6
8:5
7:4
6:3
5:2
4:1
12:5
11:4 10:3
9:2
8:1
7:0
6:0
5:0
4:0
1
0
1:0
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
17: Adders
CMOS VLSI Design 4th Ed.
16
Ladner-Fischer
15 14 13 12 11 10
15:14
13:12
15:12
11:10
9
9:8
11:8
15:8
13:8
15:8
13:0
8
7
7:6
5
5:4
7:4
7:0
11:0
6
4
3
3:2
2
1
0
1:0
3:0
5:0
9:0
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
17: Adders
CMOS VLSI Design 4th Ed.
17
Taxonomy Revisited
(f)Ladner-Fischer
(b ) S kla n sky
15
14
13
15
12
11
10
9
8
7
6
5
4
3
2
1
14
15:14
1 5 :1 4
1 3 :1 2
1 1 :1 0
9 :8
7 :6
5 :4
3 :2
13
12
1 5 :8
1 4 :1 2
1 4 :8
1 1 :8 1 0 :8
1 3 :8
7 :4
6 :4
3 :0
BrentKung
LadnerFischer
LadnerFischer
f (Fanout)
13:12
11:10
2 (5)
1 5 :1 4
1 (3)
10
9
8
7
6
5
4
3
2
1 5 :1 4
1 4 :1 3
1 3 :1 2
1 2 :1 1
1 1 :1 0
1 0 :9
9 :8
8 :7
7 :6
6 :5
5 :4
4 :3
3 :2
2 :1
1 5 :1 2
1 4 :1 1
1 3 :1 0
1 2 :9
1 1 :8
1 0 :7
9 :6
8 :5
7 :4
6 :3
5 :2
4 :1
3 :0
2 :0
1
0 (2)
0
1 :0
15:8
13:8
15:8
13:0
14
13
12
11
0 (4)
0 (1)
1 3 :1 2
1 1 :1 0
1 5 :1 2
1 4 :7
1 3 :6
1 2 :5
1 1 :4
1 0 :3
9 :2
8 :1
7 :0
6 :0
5 :0
5
4
7:6
5:4
3
2
3:2
7:4
Knowles
[4,2,1,1]
9:0
8:0
7:0
6:0
5:0
4:0
7
6
5
4
3
2
3:0
2:0
10
9
8
1
0
HanCarlson
9 :8
7 :6
5 :4
3 :2
7 :4
1 5 :8
1 :0
3 :0
7 :0
1 1 :0
9 :0
5 :0
4 :0
2 (4)
11
10
9
8
7
6
5
4
3
2
1 5 :1 4
1 4 :1 3
1 3 :1 2 1 2 :1 1
1 1 :1 0
1 0 :9
9 :8
8 :7
7 :6
6 :5
5 :4
4 :3
3 :2
2 :1
1 5 :1 2
1 4 :1 1
1 3 :1 0
1 2 :9
1 1 :8
1 0 :7
9 :6
8 :5
7 :4
6 :3
5 :2
4 :1
3 :0
2 :0
1 4 :7
1 3 :6
1 2 :5
1 1 :4
1 0 :3
9 :2
8 :1
7 :0
6 :0
5 :0
4 :0
1 5 :8
(d ) H a n -C a rlso n
15
(c) K ogge-S tone
12
1 5 :0 1 4 :0 1 3 :0 1 2 :0 1 1 :0 1 0 :0 9 :0 8 :0 7 :0 6 :0 5 :0 4 :0 3 :0 2 :0 1 :0 0 :0
HanCarlson
Knowles
[2,1,1,1]
13
1
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1 :0
Kogge3 (8)
Stone
1 5 :1 4
1 3 :1 2
1 1 :1 0
9 :8
7 :6
5 :4
3 :2
1 5 :1 2
1 3 :1 0
1 1 :8
9 :6
7 :4
5 :2
3 :0
1 5 :8
1 3 :6
1 1 :4
9 :2
7 :0
5 :0
1 :0
t (Wire Tracks)
1 5 :0 1 4 :0 1 3 :0 1 2 :0 1 1 :0 1 0 :0 9 :0 8 :0 7 :0 6 :0 5 :0 4 :0 3 :0 2 :0 1 :0 0 :0
17: Adders
1:0
0:0
5:0
9:0
New
(1,1,1)
1 5 :0 1 4 :0 1 3 :0 1 2 :0 1 1 :0 1 0 :0 9 :0 8 :0 7 :0 6 :0 5 :0 4 :0 3 :0 2 :0 1 :0 0 :0
14
0
1:0
1 (2)
15
1
3:0
7:0
11:0
1 1 :8
1 3 :0
1 5 :8
6
1 (5)
(e ) K n o w le s [2 ,1 ,1 ,1 ]
11
9:8
11:8
15:0 14:0 13:0 12:0 11:0 10:0
15
12
7
(a ) B re n t-K u n g
2 (6)
3 (9)
13
8
3 (7)
Sklansky
14
9
l (Logic Levels)
2 :0
1 2 :8
1 5 :0 1 4 :0 1 3 :0 1 2 :0 1 1 :0 1 0 :0 9 :0 8 :0 7 :0 6 :0 5 :0 4 :0 3 :0 2 :0 1 :0 0 :0
15
10
1 :0
15:12
1 5 :1 2
11
0
1 5 :0 1 4 :0 1 3 :0 1 2 :0 1 1 :0 1 0 :0 9 :0 8 :0 7 :0 6 :0 5 :0 4 :0 3 :0 2 :0 1 :0 0 :0
CMOS VLSI Design 4th Ed.
18
Summary
Adder architectures offer area / power / delay tradeoffs.
Choose the best one for your application.
Architecture
Classification Logic
Levels
Max
Tracks
Fanout
Cells
Carry-Ripple
N-1
1
1
N
Carry-Skip n=4
N/4 + 5
2
1
1.25N
Carry-Inc. n=4
N/4 + 2
4
1
2N
Brent-Kung
(L-1, 0, 0)
2log2N – 1
2
1
2N
Sklansky
(0, L-1, 0)
log2N
N/2 + 1
1
0.5 Nlog2N
Kogge-Stone
(0, 0, L-1)
log2N
2
N/2
Nlog2N
17: Adders
CMOS VLSI Design 4th Ed.
19

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