RGMII MAC RX/TX Synchronous CAPTURE WITH 16802A AGILENT LOGIC ANALYZER Pascal GRISON Application Engineer Objectives • Define a Logic Analyzer Configuration that would enable Synchronous capture of RGMII MAC interface • Ideally Capture simultaneously TX and RX RGMII MAC Interface details Bidirectional Full Duplex 125MHz Clock (for GbE) TX Side TXC (Dual Edge Clocking) TD TD0 TD1 TD2 TD3 D3..DO sent on Rising TXC D7..D4 sent on falling TXC TX_CTL TX_EN sent on Rising TXC TX_ERR sent on falling TXC RX Side RXC (Dual Edge Clocking) RD RD0 RD1 RD2 RD3 D3..DO sent on Rising RXC D7..D4 sent on falling RXC RX_CTL RXDV sent on Rising RXC RXERR sent on falling RXC Capture TX Transactions Need Synchronous Sampling: State Mode Need Double Edge Clocking: ->State Sampling at 250MHz on 125MHz Clock -> Logic Analyzer -> Demux Mode to rebuild Data RGMII TX Timings TXD[3:0] & TXEN will be Clocked on Rising edge of TXC TXD[7:4] & TXERR will be Clocked on Falling edge of TXC -> We need to use Both Edges Clocking (DEMUX Mode) Demux Sampling Mode? 2) -> TXCK FallingEdge 1) -> TXCK Rising Edge In the Demultiplex state sampling clock mode, you can demultiplex data being probed by one pod into the logic analyzer memory that is normally used for two pods. Demultiplex mode uses the master and slave clocks to demultiplex the data. When the slave clock occurs, data captured on the pod is saved into the slave latch for the other pod in the pod pair. Then, when the master clock occurs, data captured on the pod, as well as the slave latch data, are saved in logic analyzer memory. As with master/slave mode, if multiple slave clocks occur before the next master clock, only the most recently acquired slave data is saved into logic analyzer memory. Configure DEMUX Sampling Config Logic Analyzer as DEMUX STATE on TX CLOCK Rising Edge is Salve Clock and Happend First Falling Edge is Master Clock and Happend Second Master Clock Event activate Storage of one State Sample Up to 16M available (with Option 32) Configure Bus SETUP Config of Logic Analyzer buses TXCK TXDATA as 8 bit bus TXDATA[3:0] & TXEN will be Clocked on Rising edge of TXC TXDATA[7:4] & TXERR will be Clocked on Falling edge of TXC FULL DATA[7:0] + TXEN +TXERR will be stored in one memory space in logic Analyzer every clock Cycle Up to 16M TX Packet Can be Acquired (with option 32M) Overview of Logic Analyzer for TX DEMUX Current Config is the following: One Analyzer configured as one State Acquisition system to Demux and Acquire TX Packets What About RX? We Need to Acquire TX & RX Packets RX Clock behave in similar dual edge as TX Clock RGMII RX Timings RXC is derived from received Ethernet Packets (Asynchronous from TXC) RXD[3:0] & RXDV will be Clocked on Rising edge of TXC RXD[7:4] & RXERR will be Clocked on Falling edge of TXC -> We need to use Both Edges Clocking (DEMUX Mode) How to Capture RX Packets RX Clock is Asynchronous to TX Clock RXDATA and RX_CTL are muxed TX Clock CANNOT be used to Acquired RX Data Need to define two independant State Demux Acquisition System, one based on TXClock one on RXClock… Can we do this on a Single Logic Analyzer? Now Let’s Split Your 68Ch Logic Analyzer into Two 34Ch Logic Analyzers Agilent Logic Analyzers has unique capability to split themselves in Two! We now dispose of Two Independant Logic Analyzers in one Independant Channel Setup Independant Salmpling Mode Independant Clocking Independant Triggers Independant Listing/Waveforms But Also Capable of Master/Slave Triggering Correlated Mesure thanks to Independant Timestamps Common Listing/Waveforms Capability Complete TX/RX Demux Synchonous sampling System Overview TX Demux Master Trigger RX Demux Trigged from TX Trigger Common TX/RX Listing Common TX/RX Waveforms Simultaneous 4GSa/s Timing oversampling (TimingZoom) available (capture 16µs around trigger) Exemple of RGMII TX/RX Listing Demo Offline Data / Not real RGMII Capture Scope –Logic Analyzer Time Correlated Measurements Use Logic analyzer to trigger on RGMII Sequence of TX or RX Packets to Trigger Oscillosocpe Use Glitch or serial Trigger on Oscillosocpe to Trigger Logic analyzer and find matching RGMII Packet Get ALL Analog + Digital signals Displayed on single display Save ALL Analog + Digital signals Displayed on single file for post processing or Off-Line analysis Compatible with All current Agilent Scope and Logic Analyzers Easy to Setup Lan based for data transfert & control 2 BNC Cables from Triggers with autodeskew capability Automatic Fast waveform transfert from Scope to Logic Analyzer Markers correlated between instruments Exemple of Measure on DAC Digital inputs correlated with Analog Output Questions & Answers?