Unit 12 PowerPoint Slides - Sinclair Community College

Report
EET 1131 Unit 12
Shift Registers
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Read Kleitz, Chapter 13, skipping
Sections 13-6 and 13-12.
Homework #12 and Lab #12 due next
week.
Quiz next week.
Comparison of Counters & Shift Registers
4-bit Asynchronous Counter:
4-bit Synchronous Counter:
4-bit Shift Register:
Basic Shift Register Operations
A shift register is a digital circuit with two basic functions:
data storage and data movement. Some basic data
movements are illustrated here.
Data in
Data in
Data out
Data out
Serial in/shift right/serial out
Data in
Serial in/shift left/serial out
Data out
Parallel in/serial out
Data in
Data in
Data out
Serial in/parallel out
Data out
Parallel in/parallel out
Rotate right
Rotate left
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Serial-in/Serial out Shift Register
Shift registers are available in IC form or can be constructed
from discrete flip-flops, as shown here with a five-bit serialin serial-out register.
Each clock pulse will move an input bit to the next flipflop. For example, a 1 is shown as it moves across.
FF0
Serial
data
input
1
D0
C
FF1
Q0
1
D1
C
FF2
Q1
1
D2
C
FF3
Q2
1
D3
C
FF4
Q3
1
D4
Q4
1
Serial
data
output
C
CLK
CLK
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A Basic Application
One application of shift registers is conversion of serial
data to parallel form.
For example, assume the binary number 1011 is loaded
sequentially, one bit at each clock pulse.
After 4 clock pulses, the data is available at the parallel output.
FF0
Serial
data
input
1
X
0
D00
D
C
C
FF1
Q00
Q
1
0
D11
D
C
C
FF2
FF2
Q11
Q
0
11
D22
D
C
C
Q22
Q
FF3
FF3
10
D33
D
Q33
Q
11
C
C
CLK
CLK
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The 74164 Shift Register
The 74164 is an 8-bit serial in/parallel out shift register.
MR is an input, so it really
belongs on the left side with
the other inputs instead of on
the bottom with the outputs.
One of the two serial data inputs may be used as an active HIGH
enable to gate the other input. If no enable is needed, the other serial
input can be connected to VCC. The 74164 has an active LOW
asynchronous clear (MR). Data is entered on the rising edge of the
clock.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Waveforms for the 74164
Sample waveforms for
the 74164 are shown.
Notice that B acts as an
active HIGH enable for
the data on A.
MR
DSa
Serial
inputs
DSb
CLK
Q0
Q1
Q2
Q3
Outputs
Q4
Q5
Q6
Q7
Clear
Clear
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The 74165 Shift Register
The 74165 is an 8-bit parallel in/serial out shift register.
Data is loaded asynchronously when PL is LOW. Data is shifted
through the register synchronously when PL is HIGH and a rising clock
edge occurs.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Universal Shift Register
A universal shift register has both serial and parallel input
and output capability. The 74194 is an example of a 4-bit
bidirectional universal shift register.
Sample waveforms on the following slide…
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Universal Shift Register
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Some Shift Register Chips
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74164
74165
74194
74195
(8-bit
(8-bit
(4-bit
(4-bit
serial in/parallel out)
parallel in/serial out)
bidirectional universal)
parallel access)
Shift Register Applications
Shift registers can be used to delay a digital signal by a
predetermined amount.
An 8-bit serial in/serial out shift register has a 40 MHz
clock. What is the total delay through the register?
A
B
Data in
The delay for each clock
is 1/40 MHz = 25 ns
The total delay is
8 x 25 ns = 200 ns
CLK
40 MHz
SRG 8
C
Q7
Data out
Q7
25 ns
CLK
Data in
Data out
td = 200 ns
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Shift Register Applications
Data bus
A UART (Universal Asynchronous
Receiver Transmitter) is a serial-toparallel converter and a parallel to
serial converter.
Buffers
Transmitter
data register
UARTs are commonly used in small
systems where one device must
communicate with another. Parallel
data is converted to asynchronous
serial form and transmitted. The
serial data format is:
Transmitter
shift register
CLK
Receiver
data register
CLK
Serial data out
Receiver
shift register
Serial data in
Start
Bit (0)
D7
D6
D5
D4
D3
D2
D1
D0
Stop Bits (1)
t
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Cascading Shift Registers
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Most shift register chips are 4-bit or 8-bit
shift registers.
To get larger shift registers, you can cascade
two or more chips together.
For a circuit in Lab #12 you’ll need to think
about how to do this.
Shift Counters
Shift registers can form useful counters by recirculating
a pattern of 0’s and 1’s. Two important shift counters are
the ring shift counter and the Johnson shift counter.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Ring Shift Counter
The ring shift counter can be implemented with either D
flip-flops or J-K flip-flops.
FF0
Here is a 4-bit ring shift
counter constructed from a
series of D flip-flops.
Notice the feedback.
D0
FF1
Q0
D1
C
FF2
Q1
D2
C
FF3
Q2
D3
C
Q3
Q3
C
CLK
FF0
It can also be implemented
with J-K flip flops.
J0
FF1
Q0
C
K0
J
1
FF2
Q1
C
Q0
K1
J
2
FF3
Q2
C
Q1
K2
J
3
Q3
Q3
C
Q2
K3
Q3
Q3
CLK
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Ring Shift Counter
Redrawing the ring shift counter (without the clock
shown) shows why it is a “ring”.
FF0
In practical applications, the
counter is preloaded with the
desired pattern (usually a single
0 or 1).
J0
C
Q3
Q3
Q3
K3
K2
C
FF1
Q1
J3
J1
C
Q1
FF3
Q0
Q3
K0
K1
It has n states, where n = number
of flip-flops.
Q0
Q2
C
J
2
Q2
2 FF
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Ring Shift Counter
A common pattern for a ring shift counter is to load it with a single 1
or a single 0. The waveforms shown here are for an 8-bit ring shift
counter with a single 1.
CLK
1
2
3
4
5
6
7
8
9
10
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Johnson Shift Counter
FF0
The Johnson shift counter
can be made with a series
of D flip-flops
D0
FF1
Q0
C
D1
FF2
D2
Q1
C
FF3
D3
Q2
C
Q3
C
Q3
Q3
CLK
… or with a series of J-K
flip flops. Here Q3 and Q3
are fed back to the J and K
inputs with a “twist”.
FF0
J0
FF1
Q0
C
K0
J1
FF2
Q1
C
Q0
K1
J2
FF3
Q2
C
Q1
K2
J3
Q3
Q3
C
Q2
K3
Q3
Q3
CLK
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Johnson Shift Counter
Redrawing the same Johnson shift counter (without the
clock shown) illustrates why it is sometimes called as a
“twisted-ring” counter.
FF0
J0
“twist”
Q0
C
Q3
Q2
C
J
2
Q2
2 FF
Q3
Q3
K3
K2
C
FF1
Q1
J3
J1
Q1
C
K1
FF3
Q0
Q3
K0
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Johnson Shift Counter
The Johnson shift counter is useful when you need a
sequence that changes by only one bit at a time but it has a
limited number of states (2n, where n = number of stages).
The first five counts for a 4-bit Johnson counter that is
initially cleared are:
CLK
Q0 Q1 Q2 Q3
0
0 0 0 0
1
1 0 0 0
2
1 1 0 0
3
1 1 1 0
4
1 1 1 1
5
0 1 1 1
6
0 0 1 1
0 0 0 1
What are the remaining 3 states? 7
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Keyboard Encoder
The keyboard encoder is an example of where a ring
counter is used in a small system to encode a key press.
Two 74195 shift registers are connected as an 8-bit ring
counter preloaded with a single 0. As the 0 circulates in
the ring counter, it “scans” the keyboard looking for any
row that has a key closure. When one is found, a
corresponding column line is connected to that row line.
The combination of the unique column and row lines
identifies the key. The schematic is shown on the
following slide…
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Power on LOAD
SH / LD
+VCC
Ring counter
D0 D1 D2 D3
J
K
CLK
(5 kHz)
D4 D5 D6 D7
J
K
SRG 4
74HC195
C
Q0 Q1 Q2 Q3
SRG 4
74HC195
C
+V
Q4 Q5 Q6 Q7
Clock inhibit
1
2
3 4 5 6 7
ROW encoder
74HC147
1 2 4
8
1
2
3 4 5 6 7 8
COLUMN encoder
74HC147
1 2 4
Switch closure
Q
C
Q
C
D0 D1 D2 D3 D4 D5
Key code register
74HC174
C
Q0 Q1 Q2 Q3 Q4 Q5
Q
One-shots
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