Report

Probabilistic modelling of performance parameters of Carbon Nanotube transistors By Yaman Sangar Amitesh Narayan Snehal Mhatre Department of Electrical and Computer Engineering ■ Motivation Overview ■ Introduction ■ CMOS v/s CNTFETs ■ CNT Technology - Challenges ■ Probabilistic model of faults ■ Modelling performance parameters: ◻ ION / IOFF tuning ratio ◻ Gate delay ◻ Noise Margin ■ Conclusion 04/29/2014 1 Motivation Overview Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: ION / IOFF tuning ratio Gate delay Noise Margin Conclusion 04/29/2014 2 MOTIVATION: Why CNTFET? ■ ■ ■ ■ Dennard Scaling might not last long Increased performance by better algorithms? More parallelism? Alternatives to CMOS - FinFETs, Ge-nanowire FET, Sinanowire FET, wrap-around gate MOS, graphene ribbon FET ■ What about an inherently faster and less power consuming device? ■ Yay CNTFET – faster with low power 04/29/2014 3 Motivation Overview Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: ION / IOFF tuning ratio Gate delay Noise Margin Conclusion 04/29/2014 4 Carbon Nanotubes ■ CNT is a tubular form of carbon with diameter as small as 1nm ■ CNT is configurationally equivalent to a 2-D graphene sheet rolled into a tube. 04/29/2014 5 Types of CNTs ■ Single Walled CNT (SWNT) ■ Double Walled CNT (DWNT) ■ Multiple Walled CNT (MWNT) ■ Depending on Chiral angle: • Semiconducting CNT (s-CNT) • Metallic CNT (m-CNT) 04/29/2014 6 Properties of CNTs ■ ■ ■ ■ ■ Strong and very flexible molecular material Electrical conductivity is 6 times that of copper High current carrying capacity Thermal conductivity is 15 times more than copper Toxicity? 04/29/2014 7 CNTFET How CNTs conduct? ■ Gate used to electrostatically induce carriers into tube ■ Ballistic Transport 04/29/2014 8 Motivation Overview Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: ION / IOFF tuning ratio Gate delay Noise Margin Conclusion 04/29/2014 9 Simulation based Comparison between CMOS and CNT technology Circuit FET Delay (In Picoseconds) Power (In uWatts) Inverter CMOS 16.58 9.81 CNT 3.78 0.25 CMOS 24.32 20.67 CNT 5.98 0.69 CMOS 39.26 22.13 CNT 6.49 0.48 2 Input Nand 2 Input Nor 04/29/2014 10 Simulation based Comparison between CMOS and CNT technology Circuit FET Delay (In Picoseconds) Power (In uWatts) Inverter CMOS 16.58 9.81 CNT 3.78 0.25 CMOS 24.32 20.67 CNT 5.98 0.69 CMOS 39.26 22.13 CNT 6.49 0.48 2 Input Nand 2 Input Nor Better delay 04/29/2014 11 Simulation based Comparison between CMOS and CNT technology Circuit FET Delay (In Picoseconds) Power (In uWatts) Inverter CMOS 16.58 9.81 CNT 3.78 0.25 CMOS 24.32 20.67 CNT 5.98 0.69 CMOS 39.26 22.13 CNT 6.49 0.48 2 Input Nand 2 Input Nor 04/29/2014 Better delay At lower power! 12 Motivation Overview Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: ION / IOFF tuning ratio Gate delay Noise Margin Conclusion 04/29/2014 13 Challenges with CNT technology ■ Unavoidable process variations ■ Performance parameters affected ■ Major CNT specific variations ■ CNT density variation ■ Metallic CNT induced count variation ■ CNT diameter variation ■ CNT misalignment ■ CNT doping variation 04/29/2014 14 CNT density variation CNT diameter variation ■ Current variation ■ Threshold voltage variation 04/29/2014 15 CNT Misalignment ■ ■ ■ ■ Changes effective CNT length Short between CNTs Incorrect logic functionality Reduction in drive current 04/29/2014 CNT doping variation ■ May not lead to unipolar behavior 16 Metallic CNT induced count variation m-CNT s-CNT ■ ■ ■ ■ ■ Excessive leakage current Increases power consumption Changes gate delay Inferior noise performance Defective functionality 04/29/2014 Current m-CNT s-CNT Vgs 17 Removal of m-CNTFETs ■ VMR Technique : A special layout called VMR structure consisting of inter-digitated electrodes at minimum metal pitch is fabricated. M-CNT electrical breakdown performed by applying high voltage all at once using VMR. M-CNTs are burnt out and unwanted sections of VMR are later removed. ■ Using Thermal and Fluidic Process: Preferential thermal desorption of the alkyls from the semiconducting nanotubes and further dissolution of m-CNTs in chloroform. ■ Chemical Etching: Diameter dependent etching technique which removes all m-CNTs below a cutoff diameter. 04/29/2014 18 Motivation Overview Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: ION / IOFF tuning ratio Gate delay Noise Margin Conclusion 04/29/2014 19 Probabilistic model of CNT count variation due to m-CNTs Probability of grown CNT count P Ngs = ngs |N = n = n P Ngm = ngm |N = n = n ngs (n−ngs ) Cngs ps pm (n−ngm ) ngm pm Cngm ps ■ ps = probability of s-CNT ■ pm = probability of m-CNT ■ ps = 1 - pm ■ Ngs = number of grown s-CNTs ■ Ngm = number of grown m-CNTs ■ N = total number of CNTs 04/29/2014 20 Conditional probability after removal techniques ■ ■ ■ ■ ■ ■ Ns Nm prs prm qrs qrm P Ns = ns |Ngs = ngs = ngs P Nm = nm |Ngm = ngm = ngm (n -ns ) Cns qnrss prs gs (ngm -nm) Cnm qrm pnrmm = number of surviving s-CNTs = number of surving m-CNTs = conditional probability that a CNT is removed given that it is s-CNT = conditional probability that a CNT is removed given that it is m-CNT = 1 - prs = 1 -prm 04/29/2014 21 Motivation Overview Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: ION / IOFF tuning ratio Gate delay Noise Margin Conclusion 04/29/2014 22 Effect of CNT count variation on ION / IOFF tuning ratio ■ ION / IOFF is indicator of transistor leakage ■ Improper ION / IOFF → slow output transition or low output swing ■ Target value of ION / IOFF = 104 04/29/2014 23 Current of a single CNT ICNT = ps Is + pmIm µ(ICNT) = psµ( Is )+ pmµ(Im ) ■ ICNT = drive current of single CNT (type unknown) ■ Is = drive current of single s-CNT ■ Im = drive current of single m-CNT ■ ps = probability of s-CNT ■ pm = probability of m-CNT 04/29/2014 24 ION / IOFF ratio of CNTFET , + = , + ■ Ns = count of s-CNT ■ Nm = count of m-CNT ■ Is,on = s-CNT current, Vgs = Vds = Vdd ■ Is,off = s-CNT current, Vgs = 0 and Vds = Vdd ■ Im = m-CNT current, Vds = Vdd 04/29/2014 25 ION / IOFF ratio of CNTFET µ( ) µ( ) µ(, ) + µ( ) µ( ) = µ ( ) µ( ) µ(, ) + µ( ) µ( ) µ (Ns) = ps (1 - prs) N µ (Nm) = pm (1 - prm) N µ( ) 1 − (, ) + 1 − ( ) = µ ( ) 1 − (, ) + 1 − ( ) 04/29/2014 26 Effect of various processing parameters on the ratio µ(ION) / µ(IOFF) ( ) ( ) 1- prm ■ µ(ION) / µ(IOFF) is more sensitive to prm ■ µ(ION) / µ(IOFF) = 104 for prm > 1 – 10 -4 = 99.99 % for pm = 33.33% 04/29/2014 27 Motivation Overview Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: ION / IOFF tuning ratio Gate delay Noise Margin Conclusion 04/29/2014 28 Effect of CNT count variation on Gate delay Cload ∆V delay = Idrive 04/29/2014 29 Cload Vdd µ(delay) ≈ µ(Idrive ) Cload Vdd σ(delay) ≈ 2 σ(Idrive ) ) µ (Idrive σ(Idrive ) σ(delay) ≈ µ(delay) µ(Idrive ) = σ2 + σ2 + µ − µ σ(delay) μ(delay) 04/29/2014 = ps σ2s pm ps μ2s ps μs = 2 σ2s pm μ2s ps μs 30 Plot of σ delay μ(delay) σ delay µ(delay) v/s = 0.3 N = 10 N = 20 N = 40 N = 30 N = 50 04/29/2014 31 Plot of σ delay μ(delay) v/s N σ delay µ(delay) 0.9 0.2 04/29/2014 0.4 0.6 0.8 N 32 Motivation Overview Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: ION / IOFF tuning ratio Gate delay Noise Margin Conclusion 04/29/2014 33 Noise Margin of CNTFET 04/29/2014 34 VIL and VIH pFET nFET ■ βn 2 VGS − Vthn VGSn − Vthn − 2kT q + Ef q − 2e−1 = m βp 2 VGSp − Vthp − 2e−1 m + 2kT q 2 VDSp −VDS p ■ Substituting VGSn = Vin, VGSp = VDD − Vin , VDSn = Vout and VDSp = Vout − VDD ■ βn 2 Vin − Vthn Vin − Vthn − 2kT q + 2∆Ef q − 2e−1 m = ■ Differentiating with respect to Vin and substituting 04/29/2014 βp 2 2 Vin − VDD − Vthp − dVout dVin 2e−1 m + 2kT q Vout − VDD − Vout − VDD 2 = -1 35 VIL and VIH For CMOS, For CNTFET, NML = VIL - 0 NMH = VDD – VIH 04/29/2014 36 Motivation Overview Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: ION / IOFF tuning ratio Gate delay Noise Margin Conclusion 04/29/2014 37 CONCLUSION ■ Modeled count variations and hence device current as a probabilistic function ■ Studied the affect of these faults on tuning ratio and gate delay ■ Inferred some design guidelines that could be used to judge the correctness of a process ■ Mathematically derived noise margin based on current equations – better noise margin than a CMOS 04/29/2014 38