Probabilistic modelling of performance parameters of Carbon

Report
Probabilistic modelling of performance parameters of
Carbon Nanotube transistors
By
Yaman Sangar
Amitesh Narayan
Snehal Mhatre
Department of Electrical and Computer Engineering
■ Motivation
Overview
■ Introduction
■ CMOS v/s CNTFETs
■ CNT Technology - Challenges
■ Probabilistic model of faults
■ Modelling performance parameters:
◻ ION / IOFF tuning ratio
◻ Gate delay
◻ Noise Margin
■ Conclusion
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1
 Motivation
Overview
 Introduction
 CMOS v/s CNTFETs
 CNT Technology – Challenges
 Probabilistic model of faults
 Modelling performance parameters:
 ION / IOFF tuning ratio
 Gate delay
 Noise Margin
 Conclusion
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MOTIVATION: Why CNTFET?
■
■
■
■
Dennard Scaling might not last long
Increased performance by better algorithms?
More parallelism?
Alternatives to CMOS - FinFETs, Ge-nanowire FET, Sinanowire FET, wrap-around gate MOS, graphene ribbon FET
■ What about an inherently faster and less power consuming
device?
■ Yay CNTFET – faster with low power
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 Motivation
Overview
 Introduction
 CMOS v/s CNTFETs
 CNT Technology – Challenges
 Probabilistic model of faults
 Modelling performance parameters:
 ION / IOFF tuning ratio
 Gate delay
 Noise Margin
 Conclusion
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Carbon Nanotubes
■ CNT is a tubular form of carbon with diameter as small as 1nm
■ CNT is configurationally equivalent to a 2-D graphene sheet
rolled into a tube.
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Types of CNTs
■ Single Walled CNT (SWNT)
■ Double Walled CNT (DWNT)
■ Multiple Walled CNT (MWNT)
■ Depending on Chiral angle:
• Semiconducting CNT (s-CNT)
• Metallic CNT (m-CNT)
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Properties of CNTs
■
■
■
■
■
Strong and very flexible molecular material
Electrical conductivity is 6 times that of copper
High current carrying capacity
Thermal conductivity is 15 times more than copper
Toxicity?
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CNTFET
How CNTs conduct?
■ Gate used to electrostatically induce carriers into tube
■ Ballistic Transport
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 Motivation
Overview
 Introduction
 CMOS v/s CNTFETs
 CNT Technology – Challenges
 Probabilistic model of faults
 Modelling performance parameters:
 ION / IOFF tuning ratio
 Gate delay
 Noise Margin
 Conclusion
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Simulation based Comparison between CMOS and CNT technology
Circuit
FET
Delay
(In Picoseconds)
Power
(In uWatts)
Inverter
CMOS
16.58
9.81
CNT
3.78
0.25
CMOS
24.32
20.67
CNT
5.98
0.69
CMOS
39.26
22.13
CNT
6.49
0.48
2 Input Nand
2 Input Nor
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Simulation based Comparison between CMOS and CNT technology
Circuit
FET
Delay
(In Picoseconds)
Power
(In uWatts)
Inverter
CMOS
16.58
9.81
CNT
3.78
0.25
CMOS
24.32
20.67
CNT
5.98
0.69
CMOS
39.26
22.13
CNT
6.49
0.48
2 Input Nand
2 Input Nor
Better delay
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Simulation based Comparison between CMOS and CNT technology
Circuit
FET
Delay
(In Picoseconds)
Power
(In uWatts)
Inverter
CMOS
16.58
9.81
CNT
3.78
0.25
CMOS
24.32
20.67
CNT
5.98
0.69
CMOS
39.26
22.13
CNT
6.49
0.48
2 Input Nand
2 Input Nor
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Better delay
At lower power!
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 Motivation
Overview
 Introduction
 CMOS v/s CNTFETs
 CNT Technology – Challenges
 Probabilistic model of faults
 Modelling performance parameters:
 ION / IOFF tuning ratio
 Gate delay
 Noise Margin
 Conclusion
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Challenges with CNT technology
■ Unavoidable process variations
■ Performance parameters affected
■ Major CNT specific variations
■ CNT density variation
■ Metallic CNT induced count variation
■ CNT diameter variation
■ CNT misalignment
■ CNT doping variation
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CNT density variation
CNT diameter variation
■ Current variation
■ Threshold voltage variation
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CNT Misalignment
■
■
■
■
Changes effective CNT length
Short between CNTs
Incorrect logic functionality
Reduction in drive current
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CNT doping variation
■ May not lead to unipolar
behavior
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Metallic CNT induced count variation
m-CNT
s-CNT
■
■
■
■
■
Excessive leakage current
Increases power consumption
Changes gate delay
Inferior noise performance
Defective functionality
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Current
m-CNT
s-CNT
Vgs
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Removal of m-CNTFETs
■ VMR Technique : A special layout called VMR structure consisting of inter-digitated electrodes
at minimum metal pitch is fabricated. M-CNT electrical breakdown performed by applying high
voltage all at once using VMR. M-CNTs are burnt out and unwanted sections of VMR are later
removed.
■ Using Thermal and Fluidic Process: Preferential thermal desorption of the alkyls from the
semiconducting nanotubes and further dissolution of m-CNTs in chloroform.
■ Chemical Etching: Diameter dependent etching technique which removes all m-CNTs below a
cutoff diameter.
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 Motivation
Overview
 Introduction
 CMOS v/s CNTFETs
 CNT Technology – Challenges
 Probabilistic model of faults
 Modelling performance parameters:
 ION / IOFF tuning ratio
 Gate delay
 Noise Margin
 Conclusion
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Probabilistic model of CNT count variation due to m-CNTs
Probability of grown CNT count
P Ngs = ngs |N = n =
n
P Ngm = ngm |N = n =
n
ngs (n−ngs )
Cngs ps pm
(n−ngm ) ngm
pm
Cngm ps
■ ps = probability of s-CNT
■ pm = probability of m-CNT
■ ps = 1 - pm
■ Ngs = number of grown s-CNTs
■ Ngm = number of grown m-CNTs
■ N = total number of CNTs
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Conditional probability after removal techniques
■
■
■
■
■
■
Ns
Nm
prs
prm
qrs
qrm
P Ns = ns |Ngs = ngs =
ngs
P Nm = nm |Ngm = ngm =
ngm
(n -ns )
Cns qnrss prs gs
(ngm -nm)
Cnm qrm
pnrmm
= number of surviving s-CNTs
= number of surving m-CNTs
= conditional probability that a CNT is removed given that it is s-CNT
= conditional probability that a CNT is removed given that it is m-CNT
= 1 - prs
= 1 -prm
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 Motivation
Overview
 Introduction
 CMOS v/s CNTFETs
 CNT Technology – Challenges
 Probabilistic model of faults
 Modelling performance parameters:
 ION / IOFF tuning ratio
 Gate delay
 Noise Margin
 Conclusion
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Effect of CNT count variation on ION / IOFF tuning ratio
■ ION / IOFF is indicator of transistor leakage
■ Improper ION / IOFF → slow output transition or low output swing
■ Target value of ION / IOFF = 104
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Current of a single CNT
ICNT = ps Is + pmIm
µ(ICNT) = psµ( Is )+ pmµ(Im )
■ ICNT = drive current of single CNT (type unknown)
■ Is = drive current of single s-CNT
■ Im = drive current of single m-CNT
■ ps = probability of s-CNT
■ pm = probability of m-CNT
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ION / IOFF ratio of CNTFET

 , +  
=

 , +  
■ Ns = count of s-CNT
■ Nm = count of m-CNT
■ Is,on = s-CNT current, Vgs = Vds = Vdd
■ Is,off = s-CNT current, Vgs = 0 and Vds = Vdd
■ Im = m-CNT current, Vds = Vdd
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ION / IOFF ratio of CNTFET
µ( )
µ(  ) µ(, ) + µ(  ) µ(  )
=
µ ( )
µ(  ) µ(, ) + µ(  ) µ(  )
µ (Ns) = ps (1 - prs) N
µ (Nm) = pm (1 - prm) N
µ( )
 1 −  (, ) +  1 −  ( )
=
µ ( )
 1 −  (, ) +  1 −  ( )
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Effect of various processing parameters on the ratio µ(ION) / µ(IOFF)
( )
( )
1- prm
■ µ(ION) / µ(IOFF) is more sensitive to prm
■ µ(ION) / µ(IOFF) = 104 for prm > 1 – 10 -4 = 99.99 % for pm = 33.33%
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 Motivation
Overview
 Introduction
 CMOS v/s CNTFETs
 CNT Technology – Challenges
 Probabilistic model of faults
 Modelling performance parameters:
 ION / IOFF tuning ratio
 Gate delay
 Noise Margin
 Conclusion
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Effect of CNT count variation on Gate delay
Cload ∆V
delay =
Idrive
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Cload Vdd
µ(delay) ≈
µ(Idrive )
Cload Vdd
σ(delay) ≈ 2
σ(Idrive )
)
µ (Idrive
σ(Idrive )
σ(delay) ≈ µ(delay)
µ(Idrive )
=  σ2  + σ2  +  µ  − µ 
σ(delay)
μ(delay)
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=
ps σ2s pm ps μ2s
ps μs
=
2
σ2s pm μ2s
ps μs
30
Plot of
σ delay
μ(delay)


σ delay
µ(delay)
v/s


= 0.3
N = 10
N = 20
N = 40
N = 30
N = 50
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Plot of
σ delay
μ(delay)
v/s N
σ delay
µ(delay)
0.9
0.2
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0.4
0.6
0.8
N
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 Motivation
Overview
 Introduction
 CMOS v/s CNTFETs
 CNT Technology – Challenges
 Probabilistic model of faults
 Modelling performance parameters:
 ION / IOFF tuning ratio
 Gate delay
 Noise Margin
 Conclusion
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Noise Margin of CNTFET
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VIL and VIH
pFET
nFET
■
βn
2
VGS − Vthn
VGSn − Vthn −
2kT
q
+
Ef
q
−
2e−1
=
m
βp
2
VGSp − Vthp −
2e−1
m
+
2kT
q
2
VDSp −VDS
p
■ Substituting VGSn = Vin, VGSp = VDD − Vin , VDSn = Vout and VDSp = Vout − VDD
■
βn
2
Vin − Vthn
Vin − Vthn −
2kT
q
+
2∆Ef
q
−
2e−1
m
=
■ Differentiating with respect to Vin and substituting
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βp
2
2 Vin − VDD − Vthp −
dVout
dVin
2e−1
m
+
2kT
q
Vout − VDD − Vout − VDD
2
= -1
35
VIL and VIH
For CMOS,
For CNTFET,
NML = VIL - 0
NMH = VDD – VIH
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 Motivation
Overview
 Introduction
 CMOS v/s CNTFETs
 CNT Technology – Challenges
 Probabilistic model of faults
 Modelling performance parameters:
 ION / IOFF tuning ratio
 Gate delay
 Noise Margin
 Conclusion
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CONCLUSION
■ Modeled count variations and hence device current as a probabilistic function
■ Studied the affect of these faults on tuning ratio and gate delay
■ Inferred some design guidelines that could be used to judge the correctness of
a process
■ Mathematically derived noise margin based on current equations – better
noise margin than a CMOS
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