Chapter 6 Digital System Design

Report
Chapter 6
Digital System Design
242-208 Digital Systems and Logic Designs
Content
•Programmable Logic Devices (PLDs)
•PLD programming
•Combinational PLDs
•Sequential PLDs
•Field programmable gate arrays (FPGAs)
•Systematic Design
•ASM methods and charts
•Controller and data processor designs
•References
PLD: Why we need ?
Design is more economical to implement using a few
Large chips than many small chips.
Design and fabrication time for VLSI chips are extremely
long
PLD can be mage in large volume and PROGRAMMED to
implement large numbers of different low-volume
designs
What is PLD ?
An IC that contains large numbers of gates, flip-flops, etc.
that can be configured by the user to perform different
functions
Two PLD types which are :
SPLD (Simple PLD)
CPLSs (Complex PLD)
PLD programming methods:
Antifuse technology
Two metal layers sandwich a layer
of non-conductive, amorphous
silicon. When voltage is applied to
this middle layer, the amorphous
silicon is turned into polysilicon,
which is conductive.
After
PLD programming methods:
Floating gate
Current cannot passed
since no channel
for carrier charge.
Potential energy
is still high !!
High voltage applied
to the Drain,
electrons jump to
gate 1
Used in EPROM device !!
UV light strikes electrons,
causes more enough
energy for electrons to j
ump back to the channel,
The transistor starts
conducting !!
PLD programming methods:
SRAM
Combinational PLD:PROM
Programmable Read Only Memory (PROM) :
A memory device that stores data at specific locations
that can be addressed through a set of address pins.
Another view : a large array of AND gates followed by a
large array of OR gates
Combinational PLD:PLA
Programmable Logic Array (PAL) : Both arrays of logic AND
and OR are programmable
Combinational PLD:PAL
Programmable Array Logic (PAL) consists of a
programmable array of AND gates that connect to a fixed
array of OR gates
The PAL structure
allows any SOP
expression with a
defined number of
variables to be
implemented
Combinational PLD:GAL
A PAL that can be reprogrammed.
Sequential PLD:
Consists of combinational PLDs with a set of FFs.
See the diagram of IC PAL16R8.
Sequential PLD:
Implement three-bit Gray code counter using PAL16R8
Complex PLD
•Programmable PLD blocks
•Programmable
interconnects
•Electrically erasable links
Field Programmable Gate Array
Why we need FPGA ?
Limited complexity
Thousands of gates
Cheap and easy to design
Reprogrammable
Large complex functions(millions gates)
Customised design
Expensive to design (in small quantities)
Hard to design and long design cycles
Not reprogrammable
High risks
Field Programmable Gate Array
Why we need FPGA ?
Inexpensive
Easy and rapid design
Prototyping
Reprogrammable
Field Programmable Gate Array
Simple programmable Logic blocks
Massive of programmable interconnects
FPGA architecture
FPGA CLB
Look up table
FF, registers, clock storage elements
MUX
FPGA architecture
CLB
FPGA CLB with Look Up Table
LUT contains memory cells to implement logic function
Each cell holds ‘0’ or ‘1’
Programmed with outputs of truth table
Inputs select content of one of the cells as output
What is in a LUT ?
4 input – 16 outputs LUT requires 16 storage elements
with 16 latches.
FPGA CLB
Larger logic functions built by connecting many CLBs
together
Programmable routing
Connections routing signals between CLBs
Determined by SRAM cells
Programmable routing
Programmable routing
Switch matrix
FPGA : I/O Blocks
Systematic Design
For circuit design:
small circuit : gate-level design (truth tables, K
maps, etc)
large circuit : block-level design (ICs)
Larger digital systems need more abstract and
systematic design techniques.
Systematic design methodology :
Top-down approach
Partitioning
Developing overall architecture
Detailing hardware.
Systematic Design : Top-down
approach
Starting from original problem and gradually refine
it towards solution.
Steps for a top-down design procedure:
Specify the problem clearly (at global/top level
without unnecessary details).
Break the problem into smaller sub-problems.
Repeat the process until sub-problems are small
enough to be solved directly.
Systematic Design : Top-down
approach
Relevant to goal-directed approach
State goal, then find sub-goals to solve main goal.
Repeat until sub-goals are directly solvable.
Systematic Design : Partitioning
A digital system consists of two components
A control algorithm (Controller)
An architecture (Data processor)
Status condition
Commands
External
command
Control unit
(Controller)
Input
data
Data Processor
(Architecture)
Output
data
ASM
Algorithmic State Machine (ASM) Chart is a high-level
flowchart-like notation to specify the hardware
algorithms in digital systems to obtain “control” and
“data processor” units.
Major differences from flowcharts are:
only three box types:-
1) state box (similar to operation box),
2) decision box
3) conditional box
 contains exact (or precise) timing information
while flowcharts impose a relative timing order for
the operations.
Components of ASM chart
State box
 Rectangular shape
 One entry point and one exit point
Used to specify one or more operations which could
be simultaneously completed in one clock cycle.
state
binary
code
one or more
operations
Components of ASM chart
Decision box
Diamond in shape
One entry point but multiple exit points
Used to specify a number of alternative paths that can
be followed.
deciding
factors
deciding
factors
Components of ASM chart
Conditional box
Rectangle with rounded corners
Always follows a decision box and contains one or
more conditional operations that are only invoked
when the path containing the conditional box is
selected by the decision box.
conditional
operations
Example of using ASM chart
T0
Init S=0
if S equal 1 {
A=0
F =0
}
increase A
if A2 equal 1 {
E =1
if A3 equal 1 {
F=1
}
}
Initial state
0
S
1
A 0
F 0
T1
A A+1
0
1
A2
E 0
E 1
A3
T2
1
F 1
0
Register operation
Registers present in the data processor for
storing and processing data. Flip-flops (1-bit
registers) and memories (set of registers) are
also considered as registers.
The register operations are specified in either
the state and/or conditional boxes, and are
written in the form:
destination register  function(other registers)
Timing in ASM charts
Precise timing is implicitly
presented in ASM charts.
T0
Initial state
0
Each state box, together
with its immediately following
decision and conditional
boxes, occurs within one clock
cycle.
A group of boxes which
occur within a single clock
cycle is called an ASM block.
S
1
A 0
F 0
T1
A A+1
0
1
A2
E 0
E 1
A3
T2
1
F 1
0
Timing in ASM charts
Operations of ASM can be illustrated
through a timing diagram.
Two factors which must be considered are
operations in an ASM block occur at the same
time in one clock cycle
decision boxes are dependent on the status of
the previous clock cycle (that is, they do not
depend on operations of current block)
Timing in ASM charts
T0
Initial state
0
clock
1
2
3
4
5
6
states
T0
T0
T1
T1
T1
T1
input
S=0
S=1
A=1
A=2
A=3
E=0
E=0
E=1
register
values
S
1
A 0
F 0
A=0
F=0
A0
F0
Operations
T1
A A+1
0
1
A2
E 0
T2
A = A4A3A2A1
1
F 1
AA+1
AA+1
E0
E1
AA+1
AA+1
E0
E1
clock
7
8
9
10
11
12 13
states
T1
T1
T1
T2
T0
T0
input
E 1
A3
S=0
0
register
values
A=4
A=5 A=6
A=7
F=1
E=1
E=0
E=0
E=1
AA+1
F1
E0
AA+1
AA+1
E0
E1
Operations
T0
Digital system synthesis
From ASM chart, we can synthesize
Controller logic (via State Table/Diagram)
Architecture/Data Processor
Design of controller is determined from the
decision boxes and the required state
transitions.
Design requirements of data processor can
be obtained from the operations specified
with the state and conditional boxes.
Controller synthesis procedure
Step 1: Identify all states and assign suitable codes.
Step 2: Draw state diagram.
Step 3: Formulate state table using
State from state boxes
Inputs from decision boxes
Outputs from operations of state/conditional
boxes.
Step 4: Obtain state/output equations and draw
circuit.
Controller synthesis
T0
Initial state
T1
0
S
T2
1
A 0
F 0
Present
state
T1
A A+1
0
Assign codes to states:
T0 = 00
T1 = 01
T2 = 11
T0
G1 G0
1
A2
E 0
E 1
A3
T2
1
F 1
0
0
0
0
0
0
1
0
0
1
1
1
1
Next
state
inputs
outputs
S
A2 A3 G1+ G0+ T0 T1 T2
0
1
X
X
X
X
X
X
0
1
1
X
X
X
X
0
1
X
0
0
0
0
1
0
0
1
1
1
1
0
1
1
0
0
0
0
0
0
1
1
1
0
Inputs from conditions in decision boxes.
Outputs = present state of controller.
0
0
0
0
0
1
Controller synthesis
Decoder + D flip-flops
-suitable for moderately large controllers.
- procedure: use decoder to obtain individual
states; from the state table, obtain the nextstate functions by inspection.
The flip-flop input functions can be obtained directly
from the state table by inspection.
This is because for the D flip-flops,
the next state = flip-flop D input.
Decoder is then used to provide signals to represent
different states.
Controller synthesis
?
Given the state table:
G1
D Q
D Q
?
G0
2x4
decoder
T0
T1
unused
T2
clock
Present
state
G1 G0
0
0
0
0
0
1
0
0
1
1
1
1
Next
state
inputs
outputs
S
A2 A3 G1+ G0+ T0 T1 T2
0
1
X
X
X
X
X
X
0
1
1
X
X
X
X
0
1
X
0
0
0
0
1
0
0
1
1
1
1
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
The inputs of the D flip-flops
for G1 and G0 are
DG1 = T1.A2.A3
DG0 = T0.S + T1
Controller synthesis
A2
A3
G1
D Q
D Q
S
clock
G0
2x4
decoder
T0
T1
unused
T2
Data processor synthesis
Architecture is more difficult to design than
controller.
Nevertheless, it can be deduced from the ASM chart.
In particular, the operations from the ASM chart
determine:
What registers to use
How they can be connected
What operations to support
How these operations are activated.
Guidelines:
always use high-level units
simplest architecture possible.
Data processor synthesis
Various operations are:
Counter incremented (A  A + 1) when
state = T1.
Counter cleared (A  0) when state = T0
and S = 1.
E is set (E  1) when state = T1 and A2 = 1.
E is cleared (E  0) when state = T1 and
A2 = 0.
F is set (F  1) when state = T2.
Deduce:
One 4-bit register A
(e.g.: 4-bit synchronous counter with
clear/increment).
Two flip-flops needed for E and F
(e.g.: JK flip-flops).
T0
Initial state
0
S
1
A 0
F 0
T1
A A+1
0
1
A2
E 0
E 1
A3
T2
1
F 1
0
Data processor synthesis
S
start
A3
T0
Controller
T1
Clk
A2
T2
J
Q
E
Q
F
K
J
A4
A3
A2
4-bit syn.
counter A
A1
K
count
CP
clear
clock
References
[1] A. T. T. Choy, Lecture notes on CS1104-Computer
Organization.
[2] M. M. Mano, Digital Design 3rd , Prentice-Hall.
[3] John Coughlan, Lecture note on Introduction to
Programmable Logic Device.
[4] P. Cheung, Lecture note on Programmable Logic
Devices.
[5] F. Floyd, Digital Fundamentals 9th Edition, Prentice-Hall.

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