Report

Linear Dropout Regulator based Power Distribution Design under Worst Loading Amirali Shayan, Xiang Hu Christopher Pan Wenjian Yu Huawei Tsinghua University Chung-Kuan Cheng University of California San Diego Agenda Introduction and Motivation LDO based PDN Design under Worst Loading Worst case current synthesis Poles/Zeros based Methodology Experimental Results and Trade offs Conclusion Remarks Page 2 Introduction LDO design will enable: – Localized on die regulation – Relax off chip impedance – Power saving – Finer grain power management LDO design challenges – Power consumption – Area of the power MOSFET – Stability of the feedback loop – Physical design Page 3 LDO based PDN Optimization under Worst Loading Virtually eliminate 1st and 2nd droops Original Optimize Package With LDO |z| VR RPCB RPCB RPKG RPKG LDO RDIE TR RDIE TR Power saving opportunity Integrated On-die LDO Shortens the PDN loop Freq Bulk caps VRM MB caps Die LDO Package Motherboard Adv #1: Better dynamic power management through reduced response time Adv #2: Maintain low package cost while provide adequate power delivery Page 4 LDO-PDN Model of Design (1) Operation region of the power MOSFET depends on the Vds=Vext-Vout comparison with (Vgs-Vth). In our analysis, power MOSFET is in the linear region. Page 5 LDO-PDN (2) – Model Approximation On Chip Off Chip Rpar Lpar n2 Vout n3 Ron LDO Cext Rdie Iload Ron P LDO Z 1 I I closed loop Rext Cint Cdie Page 6 n4 bias bias Vdd (f) ext Z open loop (f) 1 Gain op amp Proposed Flow for Worst Case Loading LDO Optimization LDO model PDN model Zclose loop(f) Poles/Zeros LDO PDN Step Response Worst Stimuli Max Voltage Drop Optimization Page 7 Optimum PLDO / Con chip Problem Formulation Minimize Subject V to (t ) F { I 1 max P LDO step load ( s ) Z ( s )} P 0 C C on chip || I ( t ) || I 0 load step C 1 peak P = LDO Power C = Decoupling Capacitor P0 = Power limit I peak = Peak loading current of functional block Vmax = Worst voltage drop based on rogue wave Z LDO-PDN = impedance profile of ldo-pdn Page 8 LDO-PDN Output Impedance z(s) 0.009(s 2.0011)(s 0.0107 0 . 0156 i ) (s 1.8177)(s 0.0125 0.0142i) impedance zero = – Z1=-2.0011 x 1e9 – Z4,5= -0.0107 ± 0.0156i × 1e9 impedance pole = – p1=-1.8177 – p4,5= -0.0125 ± 0.0142i × 1e9 Impedance k= 0.0091 Page 9 Step Response of the LDO-PDN V (s) 1 k Z (s) s k 1 2 k 2 s p 1 k 1 s p 1 1 2 1 3 p ( p p )( p p ) 1 2 1 2 1 2 2 2 3 p ( p p )( p p ) 2 2 1 2 3 1 Page 10 3 2 3 3 p ( p p )( p p ) 3 4 s p 3 3 1 3 0 . 1011 0 . 0002 0 . 1396 i A Bi 3 ( p z )( p z )( p z ) 4 2 k 3 ( p z )( p z )( p z ) 3 3 3 1 k 2 ( p z )( p z )( p z ) 2 k k 3 p p p 1 s zz z 1 1 2 0 . 0002 0 . 1396 i A Bi Analytical Worst Step Response V (t ) k k e 1 0 . 0125 10 0 . 014 10 v t V t 9 9 0 t 2 . 12 10 9 0 t is samll v t 2 e [ A cos( t ) B sin( t )] p1t 2 0 t k t is l arg e k k e wc 1 2 p1t 0 1 [arctan( ) k ] 0 . 0017 t 2 Ae 0 . 003 0 2 A cos( t ) B sin( t ) e k k arctan( 0 . 002 / 0 . 001 ) 1 . 1 e 1 . 2048 Page 11 “Rogue Wave” Phenomenon Worst-case noise response: The maximum noise is formed when a long and slow oscillation followed by a short and fast oscillation. Rogue wave: In oceanography, a large wave is formed when a long and slow wave hits a sudden quick wave. High-frequency oscillation corresponds to the resonance of the 1st stage 0.04 0.03 Voltage (V) 0.02 0.01 0 -0.01 -0.02 -0.03 Page 12 0 0.5 Low-frequency oscillation corresponds to the resonance of the 2nd stage 1 Time (sec) 1.5 2 x 10 -6 Ideal Worst-Case PDN Noise Problem formulation I m ax v ( t ) s.t. 0 i(t) b PDN noise: t v (t ) h ( )i ( t ) d 0 h ( ): P D N im pulse response Worst-case current [Xiang ’09]: i ( t ) b for h ( ) 0 i ( t ) 0 for h ( ) 0 Zero current transition time. Unrealistic! Page 13 Rogue Wave based Current Vector Synthesis Vector based Current Activity Impedance of the PDN Partition Impulse Response FFT based convolution Max partition Synthesized Synthesized Synthesized Stimuli Stimuli Stimuli Max Voltage Drop Sign Off Page 14 14 Algorithm for Vector-based Rogue Wave Generation for i = 0 to N-window_size Begin sum each current peak of current pattern(i, i+window_size - 1) End sorted_list_des = sorting the sum of the intervals of current peak descending sorted_list_asc = sorting the sum of the intervals of current peak ascending //here is for worst-case calculating for i = 0 to N-window_size and i is increased by window_size //N is the size of impulse_reseponse if impulse_response(i) > 0 current_list = sorted_list_des else current_list = sorted_list_asc End for j = 0 to M - window_size + 1 //M is the size of current pattern idx_current = current_list(j) tmp_val = convolution of impulse_response(i, i + window_size - 1) and current_pattern(idx_current, idx_current + window_size -1) if tmp_val > max_val max_val = tmp_val max_current(i, i+window_size -1) = current_pattern(idx_current, idx_current + window_size - 1) else break end end //end of for j end //end of for i Complexity of algorithm = N log( m ) N= Impulse response size m= Current windows size Page 15 2 Vector-based Synthetic Rogue Wave Page 16 Rogue-wave Synthesis Resolution Window Sensitivity to Vmax For the rest of analysis, window resolution = 3nsec is chosen. Page 17 Vmax LDO-PDN Voltage Drop (Overshoot) Overshoot is a main concern for: Reliability of devices Hold margins Page 18 Vmin LDO-PDN Voltage Drop (Undershoot) undershoot is a main concern for: Functional failures Page 19 Optimum Configuration: Optimal Decap = 350pF Optimal Power= 20uW Noise = ~10mV Conclusion and Summary Introduced a design flow for worst case loading based on LDO poles and zeros. Proposed an optimization based on the step response and rogue wave in LDO system. Analyzed LDO power and decap area trade off in the LDO based system. Experimental result show the target voltage drop budget will be met under worst loading with optimum LDO power and decoupling value. Page 20