Networks on Chip : a very quick introduction! Jeremy Chan 11 May 2005

Report
Networks on Chip : a very
quick introduction!
Jeremy Chan
11 May 2005
Overview of Talk
• Introduction
– SoC Design Trends (communication centric
design)
• Communication Centric Design
– Application Modeling
– Energy Modeling
– NoC Optimization
• Conclusions
• Focus on communication-centric design
– Poor wire scaling
– High Performance
– Energy efficiency
• Communication architecture large proportion of energy budget
Source: Kanishka Lahiri 2004
Source: Ron Ho, Stanford 1999
SoC Design Trends
SoC Design Trends
• MPSoC: STI Cell
– Eight Synergistic
Processing
Elements
– Ring-based Element
Interconnect Bus
• 128-bit, 4
concentric rings
• Interconnect delays
becoming important
– Pentium 4 has two
dedicated drive
stages to transport
signals across chip
Source: Pham et al ISSCC 2005
The SoC nightmare
System Bus
DMA
CPU
Mem
Ctrl.
MPEG
DSP
The “Board-on-a-Chip”
Approach
Bridge
I
o
o
The
architecture
is tightly
coupled
C
Control Wires
Source: Prof Jan Rabaey CS-252-2000 UC Berkeley
Peripheral Bus
On-chip Communication
Bus-based architectures
Irregular architectures
• Bus based
interconnect
– Low cost
– Easier to Implement
– Flexible
Regular Architectures
• Networks on Chip
– Layered Approach
– Buses replaced with
Networked architectures
•
•
•
•
Better electrical properties
Higher bandwidth
Energy efficiency
Scalable
Network on Chip
Traffic
Modeling
Software
Architect
ures
Transport
Network
Separation
of concerns
Wiring
Networking
Networks on Chip
– Layered Approach
– Buses replaced with Networked architectures
•
•
•
•
Better electrical properties
Higher bandwidth
Energy efficiency
Scalable
Queuin
g
Theory
Regular Network on Chip
PE
PE
PE
PE
PE
PE
PE
PE
PE
Router
PE
Typical NoC Router
LC
FC
LC
FC
LC
FC
LC
FC
Crossbar Switch
LC
FC
LC
FC
Routing
Arbitration
NoC Issues
LC
FC
LC
FC
LC
FC
Crossbar
Switch
Routing
FC
LC
FC
LC
FC
LC
Arbitration
Irregular architectures
• Application Specific Optimization
–
–
–
–
–
Buffers
Routing
Topology
Mapping to topology
Implementation and Reuse
Regular Architectures
NoC Issues
• Architecture
– QoS Support
– What topology will
suit a particular
application?
• Fault tolerance
– Gossiping
architectures
o1 o2 o3 o4
o1
o2
o3
o4
-
-
-
-
-
I1
-
-
-
I1
-
-
-
I3
-
I1
-
I1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
BQ
GQ
…
BQ
X
GQ
slot table
arbiter
Communication Centric Design
Application
Architecture Library
Architecture / Application Model
NoC Optimisation
Configure
Refine
Evaluate
Analyse / Profile
Good?
No
Synthesis
Optimized
NoC
How are application described?
ARM:2.5ms
PPC: 2.2ms
• Few multiprocessor
embedded benchmarks
• Task graphs
– Extensively used in
scheduling research
• Each node has
computation properties
• Directed edge describes
task dependences
• Edge properties has
communication volume
SRC
15000
FFT
4000
15000
matrix
FIR
82500
4000
IFFT
40000
angle
15000
SINK
Simplifying Application Model
• With simple energy model,
Ebit = nhops x ESbit + (nhops – 1) x ELbit
– nhops proportional to energy
consumption
– Can abstract
communication design
problem to
PE1
PE2
PE3
Simple Router Energy Models
• Hu et al assume:
• Ebit = ESbit + EBbit + EWbit + ELbit
• Simplifying assumptions:
– Buffer implemented using latches and flipflops
– Negligible Internal wire energy
=> Ebit = ESbit + EBbit + EWbit + ELbit
• Router to Router Energy (minimal routing)
– Ebit= nhops x ESbit + (nhops – 1) x ELbit
Energy-Aware Task mapping
• Reduce Energy Consumption by placing
• Addressed by Hu et al 2002:
– Given a CTG and a heterogenous NoC
• Find:
– A mapping function M : tasks(T) => PEs (P)
– Assuming the tasks are already scheduled and
partitioned
• Solution formulated as a quadratic assignment
problem and solved using Branch and Bound
with heuristics
Energy Model Limitations
• Ignore:
– Static energy i.e. leakage power
– Clock energy – flip flops, latches need to be
clocked
• Buffering Energy is not free
– can consume 50-80% of total communication
architecture depending on size and depth of
FIFOs
NoC Generation
H
HDL Libraries
Graph
Representation
Routing
Algorithm
Arbiters
Flow
Control
H
R
R
R
H
NoC
Generation
Communication
Architecture
(VHDL)
• Given a parameterized NoC architecture and
library of NoC components, generate a
synthesizable HDL model.
NoC Generation
• Most packet switched routers contain
similar components that are connected
• Can be easily modularized to allow
automatic generation
Typical NoC Router
LC
FC
LC
FC
LC
FC
LC
FC
Crossbar Switch
LC
FC
LC
FC
Routing
Arbitration
Current Research
• Irregular Topology Generation
– Formulated as MILP problems
– Genetic algorithm Solution
• Buffer Allocation Problem
– Assumed Poisson Distributed Traffic
– Used Queuing Theory to Determine Ideal Buffering for
Ports => non uniform buffering depths
• Integrated solution to optimization problems
Summary
• NoC is an exciting research area that will
lead to an paradigm shift in SoC design.
• NoC research is still in infancy
– Many open research problems
– Need better application and traffic models,
new optimization techniques
• New Power, Performance, Traffic Models
being developed
Thank You

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