Microprogram control unit design

Report
Random Logic Approach
The approach described so far is called a random logic approach
and is a complicated logic design exercise.
Each design is unique and depends upon the instruction set and the
internal arrangements.
The method does not lend itself to modifications afterwards.
ITCS 3181 Logic and Computer Systems 2014 B. Wilkinson Slides8.ppt
Modification date: Nov 3, 2014
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This material is now historical and
given for completeness.
Microprogrammed Approach
Wilkes (in 1951) suggested an alternative approach for control unit
design called microprogramming.
Each elementary step is encoded into a binary pattern in much the
same way as machine instructions, and held in a memory within the
control unit.
Not widely adopted until the 1960’s but particularly convenient for
complex instruction sets. Generally not used in simple RISC designs.
Confident! Note 1951.
Wilkes, Maurice (1951). "The Best Way to Design an Automatic Computing Machine".
Report of Manchester University Computer Inaugural Conference. pp. 16–18.
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Microprogrammed Control Unit Design
Operations for each state encoded in binary in an instruction known
as a microinstruction (a small instruction)
Each microinstruction will cause the signals necessary to transfer
data from one place to another in the processor, and activates
functional units if necessary for the operation.
Microprogram – A list of microinstructions for each machine
instruction.
Microprogram held in a very high speed memory called the control
memory within the control unit of the processor.
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Microprogrammed Control Unit - Basic Concept
Machine instruction
IR register
Machine instruction fetched by special
microprogramor by hardwired logic
Control unit
Control memory
Microinstruction
Microprogram to
execute particular
machine instruction
Control signals
Obtained directly
frommicroinstruction
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Microinstruction Formats
1. Horizontal Microinstruction Format
One bit for each possible signal that might need to be generated by
any microinstruction - leads to the fastest execution:
Example
MAR  PC
Microinstruction
Destinations
0
0 1 0
Select MAR as destination
Sources
0 0
0 1 0
Other operations
0
See later
Select PC as source
Requires d bits if there are d possible destinations plus s bits if there
are s possible sources.
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2. Vertical Microinstruction Format
Mutually exclusive operations grouped together and encoded in
binary. Reduces number of bits in microinstruction. Each vertically
encoded field needs a decoder:
Microinstruction
Destination
Source
n to 2n
decoder
mto 2m
decoder
n bits
2n bits
Generally
one not used
Select
destination
Select
source
(one from 2n-1) (one from 2m-1)
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Example
Suppose there were up to 15 possible sources and destinations
(PC, MAR, MDR, IR ....). Four bits needed to specify which one:
Encoding
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
.
Destination
None
Rd
.
IR
.
.
.
R31
PC
MDR
MAR
.
Source
One pattern for no signals
None
Rs1
Rs2
.
IR15-0
Various parts of IR
IR25-0
0 (zero)
Used in Branch
4 (constant) Used to increment PC
PC
MDR
MAR
.
This is just an example of how it could be encoded, but this will be used later.
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Vertical Format Microinstruction Encoding
Example
MAR  PC
Destination
1
0
1
Source
0
4-to-16-line
decoder
15 MAR
1
0
0
0
4-to-16-line
decoder
0 15
0000010000000000
PC
0
0000000100000000
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More Complex Operations
Vertical encoding typically used to select arithmetic functions, etc.
Example
PC  PC + IR25-0
Need two sources, destination and arithmetic operation specified in
microinstruction:
Destination ALU
Source1 Source2
Other operations
Selects
Selects
Selects
Selects
destination arithmetic 1st source 2nd source
(PC above) operation (PC above) (IR
25-0 above)
(+ above)
Assumes 3 internal buses
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Possible ALU function Encoding
Encoding
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
ALU function
None (ALUout = ALUin1)
Add
Subtract
Multiply
Divide
AND
OR
Shift left
Shift right
.
Again this is just an example of how it could be encoded, but it will be used later.
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Example Encoded Microinstruction
PC  PC + IR25-0
Microinstruction
Destination
ALU fn
Source 1
Source 2
1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1
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Microinstruction Sequencing
Need a mechanism to specify next microinstruction to be executed.
Original (Wilkes) method was to hold the address of the next
microinstruction in a field within the microinstruction (so-called fouraddress instruction format):
Destination ALU
Source1 Source2
Next microinstr. address
To control memory to
fetch next microinstruction
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Microprogram counter
More convenient approach for microinstructron sequencing is to
use a microprogram counter to hold the address of the next
microinstruction just as machine instruction sequencing uses a
program counter.
Then simply increment the microprogram counter after each
microinstruction is fetched in preparation for fetching the next
microinstruction.
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Branch Microinstructions
Needed for implementing branch machine instructions.
Also useful for implementing a complex machine instruction with
microinstructions.
Original Wilkes method: Used a microinstruction with two “next
microinstruction” addresses, one for identifying state if condition true
and one for identifying the state if the condition is false.
In our case with a microprogram counter: - Only need to hold branch
target in the “next microinstruction” address field in microinstruction.
The microprogram counter holds the address of next sequential
microinstruction.
In either case, logic to select one address depending upon whether
the condition had been met.
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Branch Microinstructions
In our design, need to implement:
BL
BG
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BE
23
Rs1  0
25
Rs1  0
if Rs1 < 0
PCPC+IR 15-0
22
BNE
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Rs1  0
if Rs1 > 0
PCPC+IR 15-0
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Rs1  0
if Rs1  0
if Rs1 = 0
PCPC+IR 15-0
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PCPC+IR 15-0
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Return to fetch cycle
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All branch sequences are similar.
BL instruction
State 21
Rs1 - 0 (compare Rs1 against zero)
if (negative) goto state 22 else goto state 0
This can be simplified by arranging state 22 to be immediately after
state 21 in the microprogram.
Then state 21 reads:
Rs1 - 0 (compare Rs1 against zero)
if (positive) goto state 0
where condition is the opposite to that previously.
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Microinstruction with Conditional Branch Operations
Example
Destination ALU
Source2 Source1
Condition
Sequential execution
Unconditional jump
000
001
010
011
100
101
110
111
branch address
Never
==
!=
>=
>
<
<=
Always
Again this is just an example of how it could be encoded, but it will be used later.
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Conditional Branch Microinstruction Example
Rs1 - 0; if (negative) goto branch location
None
0000
0010
0001
0110
101
micro inst. branch address
Using previous encoding.
Number of bits in branch address depends upon maximum size of
the control memory.
Can also use two different formats, one for non-branch and one for
branch to reduce wasted space in microinstruction (first bit
specifies format).
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Other Operations
Other operations include:
Memory Read/Write
Could have one bit for either:
Destination ALU
Source2 Source1
Condition
micro inst. branch address
Memory Memory
write
read
(if 1)
(if 1)
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Memory Read
MDR  [MAR]
Destination ALU
0
Memory
Write Read
Source2 Source1
Condition
0 01 0
0
micro inst. branch address
Memory
read
Memory
Write
Memory Write
Destination ALU
[MAR]  MDR
0
Read
Source2 Source1
0 10 0
Condition
0
micro inst. branch address
Memory
write
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Final Microprogram
Fetch Cycle
Could be done in microcode or by special hardwired logic. Suppose
done in microcode starting at location 0 in control memory:
Control memory
location
T0:
T1:
T2:
T3:
MAR  PC
MDR  [MAR]
IR  MDR
PC  PC + 4
0000
0001
0010
0011
Dest
Microprogram
Fn
Src1
Src2
WR
Cond Br addr.
1010
0000
0011
1000
0000
0000
0000
0001
0000
0000
0000
0111
00
01
00
00
000
000
000
000
1000
0000
1001
1000
0... 0
0... 0
0... 0
0... 0
Subsequently, we will assume step T3 done using separate logic at same
time as step T2.
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Execute Cycle
Selecting Execute Microcode
At the end of fetch cycle, need to select the start of the
microprogram (microcode) for the specific fetched machine
instruction.
Generally, the op-code of the machine instruction can be used.
The fetched machine instruction will be in the instruction register
(IR) at this time.
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Fetch Mapping ROM
Convenient to use a read-only memory (ROM).
Opcode used to select location in mapping ROM. Contents of addressed
location holds address of microinstruction in control memory:
Instruction registers (IR)
Opcode
Mapping ROM
Control memory addr
Microcode for executing
fetched instruction
Control memory
Microinstruction
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Example
Suppose opcode pattern is 000110, and location 120 in control
memory holds first microinstruction of microprogram to execute
machine instruction.
Machine instruction
000110
Mapping ROM
Control memory
6
120
Microinstruction
120
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Selecting Execute Microcode
Need to have the step: “branch to location specified by op-code
mapping ROM” at the end of fetch cycle.
We shall choose to provide new field called here select, defined as
follows:
select
00 Next address given by microprogram counter (i.e. default for
sequential execution)
01 Next address given by op-code mapping ROM
10 Next address given by branch address field of microinstruction if
condition exists (i.e. for branch microinstructions)
Pattern 11 available and could be used to implement microinstruction
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subroutines, see later.
Next Address Select Field
Destination ALU
Memory
Write Read
Source2 Source1
Select Condition
01
micro inst. branch address
Select mapping ROM
Final microinstruction format for our design. There could be
other miscellaneous operations.
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Microprogrammed Control Unit Design
Instruction register
Machine instruction
Control unit
Control memory
Condition inputs
Next µinst.
address
logic
Microinstruction
Condition
Condition code
register
microprog
counter
micro inst.
branch addr.
Control signals
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Alternative Designs -- Clearly there are many alternative designs.
We have used mainly vertical encoding but this does lead to slower
operation. Often horizontal encoding is used with very long
microinstruction lengths (100 bits or more).
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Questions
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