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Accellera Systems Initiative Overview
Bill Read | August, 2012
Accellera Systems Initiative
Our Mission
 To provide design and verification
standards required by systems,
semiconductor, IP and design tool
companies to enhance a front-end
design automation process.
 To collaborate with its community
of companies, individuals and
organizations in delivering the
standards that lower the cost to
design commercial EDA, IC and
embedded system solutions.
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© 2012 Accellera Systems Initiative, Inc.
August, 2012
Broad Industry Support
Corporate Members
Associate Members
Diverse Membership from EDA Vendors, IP Suppliers,
Semiconductor Manufacturers and System Houses
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© 2012 Accellera Systems Initiative, Inc.
August, 2012
Why Standards?
 Design tools & methodologies continue to evolve rapidly
- Simulation
- Emulation
- IP integration
- DFx Architecting DFx
- Mixed environment
 Standards help reduce overcall cost of migrating design, IP & tools
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© 2012 Accellera Systems Initiative, Inc.
August, 2012
Accellera Systems Initiative
Board of Directors
Shishpal Rawat, Intel
Marketing Committee
Thomas Li, Springsoft
Interface (ITC)
Brian Bailey
EDA DesignLine
SystemRDL
Oren Katzir
Intel
Verilog-AMS
Scott Little
Intel
IP Tagging
Kathy Werner
Freescale
Technical Committee
Karen Pieper, Tabula
OVL
Kenneth Larson
Mentor Graphics
VIP
Hillel Miller
Freescale
Tom Alsop Intel
Administration
SystemC
Synthesis
Andres Takach
Calypto
UCIS
Richard Ho
DE Shaw
IP-XACT
Christian Fraisse
STMicrosystems
SystemC TLM
Bart Vanthournout
Synopsys
SystemC AMS
Martin Barnasconi
NXP
Supported IEEE Working Groups
1076 VHDL
Jim Lewis
SynthWorks
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1800 SystemVerilog
Karen Pieper
Tabula
© 2012 Accellera Systems Initiative, Inc.
1801 UPF
John Biggs
ARM
August, 2012
SystemC
Language
David Black
Doulos
1666 SystemC
Stan Krolikoski
Cadence
SystemC CCI
Trevor Wieman
Intel
Accellera Standards Success
Corporate
IEEE Member
Accellera formed from
VI & OVI
2000 2001
2002
2003
2004
1.0
OVL
V-AMS
SV
2005
2.0
2.1
2.2
3.1
3.1a
2006
1.8
2007
2.1
2.3
2.3
2009
2.4
2010
2.5
IEEE 1850
1.0
1.1
2.0
IEEE 1801
2.1
2.2
1.0
UCIS
1.0
VHDL
3.0
3.1
4.0
IEEE 1076
1.0 & 1.1
UVM
1.0
OCI
IEEE 1450
1.5
IP-XACT
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2.6
IEEE 1800
UPF
1.0
2011 2012
2.3.1
1.1
PSL
ITC
2008
Merger with
SPIRIT
IEEE IPR
Merger with
adopted
OSCI
© 2011-2012 Accellera Systems Initiative, Inc.
IEEE 1685
2.0
OSCI Standards Success
IEEE
1666-2005
released
OSCI
formed
OSCI
10 year
anniversary
Merger
with
Accellera
IEEE
16662011
1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012
LWG
1.0
2.0
2.1 & IEEE 1666-2005
TLM
SCV
1.0
1.0
2.0
1.0p2
SWG
AMS
2.2 & IEEE 1666-2011 2.3
Draft 1
Draft 2
AMS Study Group
Draft 1
CCI
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1.0
Requirements
© 2012 Accellera Systems Initiative, Inc.
August, 2012
1.0
Synergies and Future Opportunities
 UVM, TLM-2.0, CCI
 SystemC and UCIS
 UVM and IP-XACT
 SystemC and IPXACT
System-Level IP
Integration
System-Level
Verification
Mixed-Signal Design &
Verification
 Verilog-AMS,
SystemVerilog AMS,
SystemC AMS
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© 2012 Accellera Systems Initiative, Inc.
August, 2012
EDA and IP Design Standards and
Initiatives
SoC
Integration
IP-XACT
IP-Tagging
UCIS
Testbench
UVM
System
C
SystemVerilog
SCE-MI
OVL
Design
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SV-AMS
UPF SDF
© 2012 Accellera Systems Initiative, Inc.
OCI
VHDL
August, 2012
Verilog
Ongoing Technical Activities
Current Standards
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Verification Intellectual Property (VIP) Universal Verification Methodology (UVM) 1.1
Open Verification Library (OVL) 2.6
Verilog-AMS (V-AMS) 2.3.1
Standard Co-Emulation Modeling Interface (SCE-MI) 2.1
Unified Coverage Interoperability Standard (UCIS) 1.0
IP-XACT - Update to IEEE 1685
Intellectual Property (IP) Tagging
SystemC Synthesizable Subset Draft 1.3
SystemC Analog Mixed-Signal (AMS) 1.0
SystemC Configuration, Control & Inspection (CCI Requirements)
SystemC Language Standard
SystemRDL (launched)
Transaction Level Modeling (TLM) 1.0 and 2.0
Open Source Companions:
- UVM Reference Implementation 1.1
- SystemC Proof of Concept Library (POCL)
- SystemC Verification Library 1.0p2
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th Annual DVCon – Our flagship conference
10© 2011-2012
Accellera Systems Initiative, Inc.
Strong Relationship with IEEE
 Using Get IEEE program to allow access to EDA standards
- IEEE 1666 SystemC
- IEEE 1685 IP-XACT
 Accellera Systems Initiative Continues IEEE Standards Association
Advanced Corporate Membership
- 1076 VHDL
- 1666 SystemC Language
- 1685 IP-XACT
- 1800 SystemVerilog (SV)
- 1801 Unified Power Format (UPF)
- 1850 Property Specification Language (PSL)
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© 2012 Accellera Systems Initiative, Inc.
August, 2012
What’s Next?
 Universal Verification Methodology (UVM) 2.0
 Verilog and SystemC Analog/Mixed-Signal (AMS)
 SystemC Configuration, Control, & Inspection (CCI)
 IP Tagging
 IP-XACT
 SystemRDL
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© 2012 Accellera Systems Initiative, Inc.
August, 2012
Global Events 2013
• Silicon Valley: DVCon 2013 and North American SystemC
Users Group Meeting
• Germany: DATE 2013 and European SystemC Users Group
Meeting
• Bangalore: India SystemC Users Group Meeting, Spring
2013
• Austin, TX: DAC 2013
• Japan SystemC Users Group, July 2013
• Taiwan SystemC Users Group, Fall 2013
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© 2012 Accellera Systems Initiative, Inc.
August, 2012
Summary
 Accellera Systems Initiative is the standards body for frontend design and IP integration
 Ongoing Integration of Accellera and OSCI
 Strong collaborative relationship With the IEEE
A robust organization serving the electronics industry since 1987!
www.accellera.org
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© 2011-2012 Accellera Systems Initiative, Inc.
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© 2012 Accellera Systems Initiative, Inc.
August, 2012
Acronyms & Definitions
 AMS: Analog/Mixed Signal
 CCI: Configuration, Control & Inspection
 DVCon: Design & Verification Conference
 EDA: Electronic Design Automation
 GET: Free IEEE LRM download program
 IC: Integrated Circuit
 IP: Intellectual Property
 IPR: Intellectual Property Rights
 IP-XACT: Metadata standard for IP integration
 IEEE: Institute of Electrical and Electronics
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




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Engineers
ITC: Interface Technical Committee
LWG: Language Working Group
OCI: Open Compression Interface
OSCI: Open SystemC Initiative
OVI: Open Verilog International
OVL: Open Verification Library
© 2012 Accellera Systems Initiative, Inc.
 PSL: Property Specification Language
 SDF: Standard Delay Format
 SC: SystemC
 SCV: SystemC Verification
 SPIRIT: Structure for Packaging, Integrating,
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








and Reusing IP within Tool-flows
SV: SystemVerilog
SWG: Synthesis Working Group
TLM: Transaction-Level Modeling
UCIS: Unified Coverage Interoperability
Standard
UPF: Unified Power Format
UVM: Universal Verification Methodology
V-AMS: Verilog-Analog/Mixed Signal
VHDL: VHSIC Hardware Description Language
VI: VHDL International
VIP: Verification Intellectual Property
August, 2012
Recent Accomplishments
• Completed the merger to form the Accellera Systems Initiative
• Hosted two SystemC User Group meetings in Taiwan
• Held a session at IP-SOC in Grenoble, France about our EDA and IP
Standards Roadmap
• Published SystemC AMS extensions white paper
• Completed next revision of the SystemC LRM, IEEE 1666-2011, which is
available for free download
• Continued interest in our IEEE 1685 (IP-XACT) standard with over 4000
free downloads to date
• Released Video Tutorial "Software-Driven Verification Using TLM-2.0
Virtual Platforms“
• Released Unified Coverage Interoperability Standard (UCIS) 1.0
• Released the SystemC 2.3 Library
• Accellera Systems Initiative Technical Achievement and Leadership
Awards
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© 2012 Accellera Systems Initiative, Inc.
August, 2012

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