******* Embedded Processors

Report
Lecture 2
ARM MPU Subsystem
NCHUEE 720A Lab
Prof. Jichiang Tsai
Cortex-A8 Subsystem
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The Microprocessor Unit (MPU) subsystem
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Handles transactions between the ARM core (ARM®
Cortex™-A8 Processor), the L3 interconnect, and the
interrupt controller (INTC)
Integrates the ARM® Cortex™-A8 Processor with additional
logic for protocol conversion, emulation, interrupt handling,
and debug enhancements
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Cortex™-A8 is an ARMv7 compatible, dual-issue, in-order execution
engine with integrated L1 and L2 caches
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With NEON™ SIMD Media Processing Unit
Provides a high processing capability for mobile multimedia acceleration
Communicates through an AXI bus with the AXI2OCP bridge
Receives interrupts from the MPU subsystem interrupt controller (MPU
INTC)
NCHUEE 720A Lab
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Cortex-A8 Subsystem (cont.)
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AXI2OCP bridge:
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Includes the VFP (Vector Floating Point) coprocessor which implements
the VFPv3 architecture and is fully compliant with IEEE 754 standard
Uses the AXI (Advanced eXtensible Interface) protocol configured to 128bit data width
Includes the Embedded Trace Macrocell (ETM) support for debugging
Implements the ARMv7 debug with watch-point and breakpoint registers
and 32-bit Advanced Peripheral Bus (APB) slave interface to CoreSight
debug systems
Allows communication between the ARM (AXI), the INTC (OCP), and the
modules (OCP L3)
I2Async bridge
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An asynchronous interface providing an asynchronous OCP (Open Core
Protocol) to OCP interface
Between the AXI2OCP bridge within the MPU subsystem and the T2Async
bridge external to the MPU subsystem
NCHUEE 720A Lab
Prof. Jichiang Tsai
Cortex-A8 Subsystem (cont.)
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Clock Divider
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An Interrupt Controller is included
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Handles the module interrupts
Support up to 128 interrupt requests
The MPU allow the Debug Sub-system access to the CortexA8 debug
and emulation resources, including the Embedded Trace Macrocell
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Provides the required divided clocks to the internal modules
Has a clock input from SYSCLK2 fed by the power, reset, and clock
management (PRCM) module
The in-circuit emulator is fully compatible with CoreSight Architecture and
enables debugging capabilities
The MPU has three functional clock domains
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Including a high-frequency clock domain used by the Cortex™-A8
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The high-frequency domain is isolated from the rest of the system by
asynchronous bridges
NCHUEE 720A Lab
Prof. Jichiang Tsai
Cortex-A8 Subsystem (cont.)
NCHUEE 720A Lab
Prof. Jichiang Tsai
Cortex-A8 Subsystem (cont.)
NCHUEE 720A Lab
Prof. Jichiang Tsai
Clock and Reset Distribution
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Clock Distribution
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An embedded DPLL (Digital Phase-Locked Loop) sources the
clock for the ARM Cortex-A8 processor
A clock divider is used for deriving the clocks for other
internal modules
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All major modules are clocked at half the frequency of the ARM core.
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The divider of the output clock can be programmed
The frequency is relative to the ARM core
The clock generator generates the following functional clocks:
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ARM (ARM_FCLK): The core clock
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The base fast clock routed internally to the ARM logic and internal RAMs,
including NEON, L2 cache, the ETM core (emulation), and the ARM core
AXI2OCP Clock (AXI_FCLK): Half the frequency of ARM_FCLK
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The OCP interface thus performs at one half the frequency of ARM
NCHUEE 720A Lab
Prof. Jichiang Tsai
Clock and Reset Distribution (cont.)
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Interrupt Controller Functional Clock (MPU_INTC_FCLK):
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ICE-Crusher Functional Clock (ICECRUSHER_FCLK):
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Operates on the APB interface, using the ARM core clocking
This clock is half the frequency of the ARM clock (ARM_FCLK)
I2Async Clock (I2ASYNC_FCLK):
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Part of the INTC module
Half the frequency of the ARM clock (ARM_FCLK)
Half the frequency of the ARM clock (ARM_FCLK)
Matches the OCP interface of the AXI2OCP bridge
The second half of the asynchronous bridge (T2ASYNC) is clocked
directly by the PRCM with the core clock
T2ASYNC is not part of the MPU subsystem.
Emulation Clocking: Distributed by the PRCM module
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Asynchronous to the ARM core clock (ARM_FCLK)
Can run at a maximum of 1/3 the ARM core clock
NCHUEE 720A Lab
Prof. Jichiang Tsai
Clock and Reset Distribution (cont.)
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Clock and Reset Distribution (cont.)
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Reset Distribution
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Resets to the MPU subsystem are provided by the PRCM
Controlled by the clock generator module
NCHUEE 720A Lab
Prof. Jichiang Tsai
Clock and Reset Distribution (cont.)
NCHUEE 720A Lab
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ARM Subchip
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The ARM Cortex-A8 processor incorporates the
technologies available in the ARM7™ architecture
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NEON™ for media and signal processing
Jazelle™ RCT for acceleration of realtime compilers
Thumb®-2 technology for code density
The VFPv3 floating point architecture
The AXI bus interface is the main interface to the ARM
system bus
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Performs L2 cache fills and noncacheable accesses for both
instructions and data.
Supports 128bit and 64-bit wide input and output data buses
Supports multiple outstanding requests on the AXI bus
NCHUEE 720A Lab
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ARM Subchip (cont.)
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Supports a wide range of bus clock to core clock ratios
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The bus clock is synchronous with the core clock
Special secure monitor functions are supported
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Allows access to certain ARM core registers in privileged
mode
Provides functions to write to CP15 Registers
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Auxiliary Control Register, Nonsecure Access Control Register, and
the L2 Cache Auxiliary Control Register
NCHUEE 720A Lab
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ARM Subchip (cont.)
NCHUEE 720A Lab
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Interrupt Controller
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The Host ARM Interrupt Controller (AINTC) is
responsible for
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Prioritizing all service requests from the system peripherals
Generating either nIRQ or nFIQ to the host
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Via the AXI port through an AXI2OCP bridge
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The type of the interrupt (nIRQ or nFIQ) and the priority of the
interrupt inputs are programmable.
Runs at half the processor speed
Has the capability to handle up to 128 requests
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Level sensitive interrupts inputs
Individual priority for each interrupt input
Each interrupt can be steered to nFIQ or nIRQ
Independent priority sorting for nFIQ and nIRQ
NCHUEE 720A Lab
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Power Management
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The MPU subsystem is divided into 4 power domains
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Controlled by the PRCMTIMERS
MPU subsystem domain
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MPU NEON domain
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ARM NEON accelerator
CORE domain
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ARM, AXI2OCP, I2Asynch Bridge, ARM L1 and L2 periphery logic and
array, ICE-Crusher, ETM, APB modules
L1 and L2 array memories have separate control signals into the in
MPU Subsystem, thus directly controlled by PRCM
MPU interrupt controller
EMU domain
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EMU: ETB (Embedded Trace Buffer) and DAP (Debug Access Port)
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Power Management (cont.)
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Power Management (cont.)
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Each power domain can be driven by the PRCM in 4
different states
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For each domain, the PRCM manages all transitions
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Depending on the functional mode required by the user
By controlling domain clocks, domain resets, domain logic
power switches and memory power switches
The major part of the MPU subsystem belongs to the
MPU power domain
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The modules inside this power domain can be off at a time
when the ARM processor is in an OFF or standby mode
NCHUEE 720A Lab
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Power Management (cont.)
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For the MPU to be on, the core power must be on
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Device power management does not allow INTC to go to OFF
state when MPU domain is on
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Active or one of retention modes
The NEON core has independent power off mode when
not in use
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IDLE/WAKEUP control is managed by the clock generator block but
initiated by the PRCM module
Enabling and disabling of NEON can be controlled by software
The L1 cache memory does not support retention mode
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The ARM L2 can be put into retention independently of the
other domains
NCHUEE 720A Lab
Prof. Jichiang Tsai
Power Management (cont.)
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The supported operational power modes
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All other combinations are illegal
The ARM L2, NEON, and ETM/Debug can be powered
up/down independently
The APB/ATB ETM/Debug column refers to all three features
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ARM emulation, trace, and debug
The MPU subsystem must be in a power mode where the
MPU power domain, NEON power domain, debug power
domain, and INTC power domain are in standby, or off state
NCHUEE 720A Lab
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Power Management (cont.)
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MPU Power Mode Transitions
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Basic Power-On Reset
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Initial power-up and wakeup from device off mode
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Reset the INTC and the MPU subsystem modules
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CORE_RST and MPU_RST
The clocks must be active during the MPU reset and CORE reset
MPU Into Standby Mode
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Initial power-up and wakeup from device Off mode
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The core initiates entering into standby via software only (CP15 WFI)
MPU modules requested internally of MPU subsystem to enter idle
MPU is in standby output asserted for PRCM
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All outputs guaranteed to be at reset values
PRCM can now request INTC to enter into idle mode
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Acknowledge from INTC goes to PRCM
NCHUEE 720A Lab
Prof. Jichiang Tsai
MPU Power Mode Transitions (cont.)
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MPU Out Of Standby Mode
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Initial power-up and wakeup from device Off mode
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PRCM must start clocks through DPLL programming
Detect active clocking via status output of DPLL
Initiate an interrupt through the INTC to wake up the ARM core
from STANDBYWFI mode
MPU Power On From a Powered-Off State
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MPU Power On, NEON Power On, Core Power On (INTC)
should follow the ordered sequence per power switch daisy
chain to minimize the peaking of current during power-up
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The core domain must be on, and reset, before the MPU can be reset
Follow the reset sequence as the Basic Power-On Reset
NCHUEE 720A Lab
Prof. Jichiang Tsai
ARM7 Architecture
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From the programmer’s point of view, the ARM7 can be in
one of two states
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ARM state executes 32-bit, word-aligned ARM instructions
THUMB state operates with 16-bit, half-word-aligned THUMB
instructions
ARM7 views memory as a linear collection of bytes
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Numbered upwards from zero
Bytes 0 to 3 hold the first stored word, bytes 4 to 7 the
second and so on
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ARM7 can treat words in memory as being stored either in BigEndian or Little-Endian format
ARM7 supports byte (8-bit), half-word (16-bit) and word (32bit) data types
NCHUEE 720A Lab
Prof. Jichiang Tsai
ARM7 Architecture (cont.)
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Operating modes
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User (usr): The normal ARM program execution state
FIQ (fiq): To support a data transfer or channel process
IRQ (irq): Used for general-purpose interrupt handling
Supervisor (svc): Protected mode for the operating system
Abort mode (abt): Entered after a data or instruction prefetch
abort
System (sys): A privileged user mode for the operating system
Undefined (und): Entered when an undefined instruction is
executed
Mode changes may be made under software control, or may be
brought about by external interrupts or exception processing
NCHUEE 720A Lab
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ARM7 Architecture (cont.)
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Registers
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ARM7 has a total of 37 registers
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31 general-purpose 32-bit registers and six status registers
These cannot all be seen at once
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The processor state and operating mode dictate which registers are
available to the programmer
In ARM state, 16 general registers and one or two status
registers are visible at any one time
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In privileged (non- User) modes, mode-specific banked registers are
switched in.
The ARM state register set contains 16 directly accessible registers
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R0 to R15
All of these except R15 are general-purpose, and may be used to hold
either data or address values
NCHUEE 720A Lab
Prof. Jichiang Tsai
ARM7 Architecture (cont.)
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There is a seventeenth register used to store status
information
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Register 16 is the CPSR (Current Program Status Register)
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Register 14 is used as the subroutine link register
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This receives a copy of R15 when a subroutine is invoked
All other times, it may be treated as a general-purpose register
The corresponding banked registers R14_svc, R14_irq, R14_fiq,
R14_abt and R14_und are aslo used to hold the return values of R15
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This contains condition code flags and the current mode bits
When interrupts and exceptions arise, or when branch and link
instructions are executed within interrupt or exception routines
Register 15 holds the Program Counter (PC)
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In ARM state, bits [1:0] of R15 are zero and bits [31:2] contain the PC
In THUMB state, bit [0] is zero and bits [31:1] contain the PC
NCHUEE 720A Lab
Prof. Jichiang Tsai
ARM7 Architecture (cont.)
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FIQ mode has seven banked registers mapped to R8-R14
(R8_fiq-R14_fiq)
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in IRQ mode, Supervisor, Abort and Undefined each have two
banked registers mapped to R13 and R14
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In ARM state, many FIQ handlers do not need to save any registers
Allowing each of these modes to have a private stack pointer and link
registers
The THUMB state register set is a subset of the ARM state set
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The programmer has direct access to eight general registers, R0–R7,
as well as the Program Counter (PC), a stack pointer register (SP), a
link register (LR), and the CPSR.
There are banked stack pointers, link registers and Saved Process
Status Registers (SPSRs) for each privileged mode
NCHUEE 720A Lab
Prof. Jichiang Tsai
ARM7 Architecture (cont.)
NCHUEE 720A Lab
Prof. Jichiang Tsai
ARM7 Architecture (cont.)
NCHUEE 720A Lab
Prof. Jichiang Tsai
ARM7 Architecture (cont.)
NCHUEE 720A Lab
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ARM7 Architecture (cont.)
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The ARM7 contains a Current Program Status Register (CPSR)
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Plus five Saved Program Status Registers (SPSRs) for use by exception
handlers
These register’s functions are
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Hold information about the most recently performed ALU operation
Control the enabling and disabling of interrupts
Set the processor operating mode
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ARM7 Architecture (cont.)
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ARM7 Architecture (cont.)
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An exception arises when the normal flow of program
execution is interrupted
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e.g., processing is diverted to handle an interrupt from a
peripheral
The processor state just prior to handling the exception must
be preserved
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The program flow can be resumed when the exception routine is
completed
The system uses the banked core registers to save the current state.
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The old PC value and the CPSR contents are copied into the appropriate
banked R14 (LR) and SPSR registers
The PC and mode bits in the CPSR are adjusted to the value
corresponding to the type of exception being processed
NCHUEE 720A Lab
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ARM7 Architecture (cont.)
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There are seven types of exceptions
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Each has a fixed priority and a privileged processor mode
NCHUEE 720A Lab
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