Report

By: Ali Mesgarani Electrical and Computer Engineering University of Idaho 1 Outline Motivation and goals Background New ADC topologies proposed for high speed, low power and medium resolution Asynchronous binary search ADC Pipeline binary search ADC Conclusion 2 Motivation ADCs are key design blocks in modern microelectronic systems. More signal-processing functions are implemented in the digital domain. Noise immunity Low power Easy to design using CAD tools Reproducibility, … Today’s high speed communication systems have increased the demand for increased data rates, small area, and low power consumption. High speed ADCs have significant importance in today’s digital signal processing and communication systems. Designing energy efficient A/D converters by developing new architectures and circuits to take full advantage of what the modern process technologies have to offer. 3 Outline Motivation and goals Background New ADC topologies proposed for high speed, low power and medium resolution Asynchronous binary search ADC Pipeline binary search ADC Conclusion 4 Why do we need A/D converters? The real world is analog, but easier to process digital data. Speech, image, … Digital data needs to be carried on an analog signal Signal received at the antenna must be digitized. Analog signals contain too much unnecessary amount of data ADC samples the data and splits it into finite information ADC converts analog information to digital information 5 ADC at receiver in a link DAC ADC 6 Analog to digital converter (ADC) Analog Digital Sample & Hold Quantization fsample 7 Quantization 111 110 101 100 Digital Output Digital Output Dout 111 VFSR ΔV, VLSB 011 010 110 101 100 011 010 001 001 000 000 Vref 8 4 Vref 8 7 Vref 8 1 2 3 4 5 6 7 8 Time Analog Input Vin 8 High speed ADC applications Ultra Wide Band (UWB) communication High Speed Serial Links Digital Oscilloscope Hard Disk Drive Read-Channel Digital TV Wireless Personal Area Network (WPAN) Software Defined Radio 9 High speed ADC applications Reference Resolution (bits) Speed (GS/s) Power (mW) Application Park, CICC’06 5.0 3.50 227.0 UWB Chan, JSSC’08 7.0 5.00 - UWB Verbruggen, JSSC’10 6.0 2.60 2.2 UWB Harwood, ISSCC ‘07 4.5 12.50 - Serial links Cao, JSSC ‘10 6.0 10.00 10000.0 Serial links Uyttenhove, JSSC ‘03 6.0 1.30 545.0 Hard disk drive read-channel Cao, ISSCC ‘08 6.0 1.30 600.0 Hard disk drive read-channel Poulton, ISSCC ’02 8.0 4.00 4600.0 Digital oscilloscope Poulton, ISSCC ‘03 8.0 20.00 10000.0 Digital oscilloscope Schvan,ISSCC ‘8 10.0 1.35 420.0 Digital TV Van der Plas,ISSCC ‘06 4.0 1.25 2.5 WPAN 10 ADC topologies Flash Pipeline Successive Approximation Register (SAR) Sub-ranging Ramp Single slope Dual slope Delta-Sigma 11 Flash ADC N-bit flash: 2N -1 comparators Vin connected with 2N -1 comparators in parallel Comparators connected to resistor string Vref Vin R/2 Over range R R D0 R R (2N-1) to N encoder D1 R DN-1 R R R/2 12 Flash ADC pros and cons Pros Very fast Cons Area and power increase exponentially with resolution Input capacitive loading on Vin Noise Offset Jitter sensitivity 13 Pipelined A/D converters Widely used where high resolution and high throughput is required A pipeline A/D converter is a multi-step amplitude quantizer Cascade of stages of low-resolution analog-to-digital converters Trades latency for speed 14 Pipeline A/D converters Coarse quantizer 15 Pipeline A/D converter Pros and Cons Pros High throughput Easy upgrade to higher resolutions Cons Latency High demands on speed and gain of amplifier(s) High power 16 SAR ADC Based on binary search Consisted of a comparator, N-bit DAC, binary search logic Compare VD/A with input signal Vin Modify VD/A by D0D1D2…DN-1 until closest possible value to Vin is reached Sequential converter Vin S&H VD/A Logic D0 D1 DAC DN-1 Successive Approximation Register (SAR) ADC Vref 17 3-bit SAR ADC example 111 7 Vref 8 110 110 VD/A 101 Vin 011 010 Vref 1. 3. 2. Iterations final result 011 010 001 8 101 100 100 4 Vref 8 111 001 000 18 SAR ADC pros and cons Pros Small area Low power Cons Low speed: N clock cycle for N-bit SAR ADC. Complex clock generation at high sampling rates: A 6 bit 300MS/s SAR ADC requires 2.1 GHz clock generator with low skew. Clock generator consumes more power than the ADC itself! 19 Resolution vs sampling rate of ADCs SAR ADCs are the most energy efficient ADC topologies but low speed Can we design ADCs with efficiency of SAR and speed of flash converters. 20 Asynchronous SAR ADC Problems with SAR The logic delay in the feedback takes up to 75% of clock cycle Complex clock generation Solution: Asynchronous SAR/Binary Search ADC No complex clock gen. No binary search logic 4.5/8 ABS ADC 0 0 1 1 1 0 21 Asynchronous SAR ADC Unroll feedback loop N comparators are used. Asynchronous clock is generated from MSB to LSB. Speed is limited by N comparator delays and DAC delays 22 Asynchronous SAR pros and cons Pros Can operate faster than conventional SAR No need for high speed clock generation Cons Offset between comparators High resolution cannot be achieved like SAR because of the offset. Larger area 23 Outline Motivation and goals Background New ADC topologies proposed for high speed, low power and medium resolution Asynchronous binary search ADC Pipeline binary search ADC Conclusion 24 Proposed ADC topologies Asynchronous topologies 2-bit/stage Asynchronous Binary Search (ABS) ADC Hybrid topologies Pipeline Binary Search (PBS) ADC 25 Proposed ADC topologies Asynchronous topologies 2-bit/stage Asynchronous Binary Search (ABS) ADC Hybrid topologies Pipeline Binary Search (PBS) ADC 26 2-bit/stage ABS ADC In a typical asynchronous SAR/binary search ADC speed is limited by N comparator, N DAC delays How to speed up? Resolve two bits in each stage (2-bit flash) Speed limited by N/2 comparator delays and DAC delays. Speed improvement by two times Penalty Power consumption increases by 1.5 times 27 2-bit/stage ABS ADC Operation Use a 2bit flash quantizer in each stage (3 comparators) Break the reference into 4 intervals. Combines sub-ranging and asynchronous processing ideas. Break the flash ADC operation into multiple steps =9.5/16 =9.5/16 0 0 10/16 Asynch. CLK =9.5/16 =9.5/16 1 0 9/16 Asynch. CLK =9.5/16 =9.5/16 1 8/16 1 Asynch. CLK 28 2-bit/stage ABS ADC implementation φ1a C 1a φ1b From φ1b MUX SH -+ φ1a φ1b + φ1bb Vin 16 64 SH -+ φ1a φ1b + φ1bb Va3 -+ φ1a en2 + - Vin SH Va2 en2b -+ φ1a en2 + - Vin SH Va1 en2b -+ φ1a en2 + - en2,en2b Vin en2b a1,a2,a3,a4 SH Vb3 d1,d0 -+ φ1a en3 + en3b Vin SH Vb2 -+ φ1a en3 + en3b Vin SH Vb1 Encoder Logic φ1bb Vin 32 64 SH Set2[0..15,0..2] 16:1 Set Multiplexer φ1a φ1b + - Vin Asynchronous Timing Generator -+ d3,d2 Set1[0..3,0..2] Binary Search and Encoder Logic d5,d4 4:1 Set Multiplexer SH Vref,LO φ1a Asynchronous Timing Generator Vin 48 64 Resistive Ladder Vref,HI Binary Search and Encoder Logic Vin -+ φ1a en3 + - en3,en3b en3b φ1a φ1b en2 en3 data XXXXX latch d5d4XXXX d5d4d3d2XX d5d4d3d2d1d0 latch XXXXXX XXXXd1d0 29 2-bit/stage ABS ADC simulation result Parameters Value Process RF CMOS, IBM Feature size (nm) 90 Resolution (bits) 6 Supply (V) 1.2 Sampling rate (MS/s) 900 SNDR (dB) 35.82 Power (mW) 3.8 FoM (fJ/conv.step) 75 30 Proposed ADC topologies Asynchronous topologies 2-bit/stage Asynchronous Binary Search (ABS) ADC Hybrid topologies Pipeline Binary Search (PBS) ADC 31 Pipelined Binary Search ADC How can we further speed up the binary search operation of Successive Approximation Register ADC? Can we operate the Successive approximation algorithm in pipeline fashion? By combining SAR and Pipeline architectures better performance than proposed ABS ADC were achieved. Two new topologies of PBS are developed. 32 Pipeline Binary Search (PBS) ADC SAR-ADC loop has to be unrolled. Sampled input signal has to be delayed by an analog delay line. N-comparators and (n-1) digital to analog converters (DACs) have to be used Speed is limited to 1 comparator delay and DAC delays How to delay an analog signal? 33 How to delay the analog signal? Digital delay can be easily implemented using a D-latch or DFF Analog delay line is implemented by interleaved sampling of the analog signal Example: 2-clock cycle analog delay 34 6 bit, PBS ADC Circuit Implementation No opamp is used in this pipeline ADC Lower power, higher speed 35 Layout for the PBS1 ADC DACs R-String Comparator Sample&Holds Clock ditribution 36 Simulation result for PBS1 ADC Parameters Value Process LLLVT CMOS, UMC Feature size(nm) 65 Resolution (bits) 6 Supply (V) 1.2 Sampling rate (GS/s) 1.5 SNDR (dB) 35.6 Power (mW) 5.8 FoM (fJ/conv.step) 78 37 Comparison with state of the art ADCs ISSCC’8 JSSC’10 TCAS I’10 CICC ‘10 This work:PBS I ADC This work:ABS ADC Technology (nm) 130 65 65 40 65 90 Resolution (bits) 6 6 5 6 6 6 # of channels 2 2 1 1 1 1 Sampling Rate (GS/s) 1.20 1.00 0.70 1.25 1.20 1.50 0.90 Peak SNDR (dB) 35.0 31.5 29.0 30.5 36.0 35.8 36.1 SNDR (dB) 28.0 28.0 26.9 26.5 35.6 35.6 35.8 Power (mW) 32.0 6.3 2.0 6.1 4.8 5.8 4.3 Supply (V) 1.0 1.2 1.0 1.0 FoM (fJ/cs) 980 210 116 178 1.2 81 1.2 78 74 38 Summary High speed and low power analog to digital converters are essential part of many communication and signal processing applications In this research new ADC topologies that take the advantage of energy efficiency of SAR ADCs while enabling high speed operation compared with conventional SAR ADCs architectures is proposed. A new 2 bit/stage ABS ADC was introduced Twice as fast as conventional ABS ADCs A new ADC concept and implementation (PBS ADC) was introduced Enables binary search operation in a pipelined fashion Application of asynchronous ADCs as quantizers for high resolution ADCs 39 Thank you for your attention Q&A 40